Continuous-Time and Companding Digital Signal Processors Using Adaptivity and Asynchronous Techniques

The fully synchronous approach has been the norm for digital signal processors (DSPs) for many decades. Due to its simplicity, the classical DSP structure has been used in many applications. However, due to its rigid discrete-time operation, a classical DSP has limited efficiency or inadequate resolution for some emerging applications, such as processing of multimedia and biological signals. This thesis proposes fundamentally new approaches to designing DSPs, which are different from the classical scheme. The defining characteristic of all new DSPs examined in this thesis is the notion of "adaptivity" or "adaptability." Adaptive DSPs dynamically change their behavior to adjust to some property of their input stream, for example the rate of change of the input. This thesis presents both enhancements to existing adaptive DSPs, as well as new adaptive DSPs. The main class of DSPs that are examined throughout the thesis are continuous-time (CT) DSPs. CT DSPs are clock-less and event-driven; they naturally adapt their activity and power consumption to the rate of their inputs. The absence of a clock also provides a complete avoidance of aliasing in the frequency domain, hence improved signal fidelity. The core of this thesis deals with the complete and systematic design of a truly general-purpose CT DSP. A scalable design methodology for CT DSPs is presented. This leads to the main contribution of this thesis, namely a new CT DSP chip. This chip is the first general-purpose CT DSP chip, able to process many different classes of CT and synchronous signals. The chip has the property of handling various types of signals, i.e. various different digital modulations, both synchronous and asynchronous, without requiring any reconfiguration; such property is presented for the first time CT DSPs and is impossible for classical DSPs. As opposed to previous CT DSPs, which were limited to using only one type of digital format, and whose design was hard to scale for different bandwidths and bit-widths, this chip has a formal, robust and scalable design, due to the systematic usage of asynchronous design techniques. The second contribution of this thesis is a complete methodology to design adaptive delay lines. In particular, it is shown how to make the granularity, i.e. the number of stages, adaptive in a real-time delay line. Adaptive granularity brings about a significant improvement in the line's power consumption, up to 70% as reported by simulations on two design examples. This enhancement can have a direct large power impact on any CT DSP, since a delay line consumes the majority of a CT DSP's power. The robust methodology presented in this thesis allows safe dynamic reconfiguration of the line's granularity, on-the-fly and according to the input traffic. As a final contribution, the thesis also examines two additional DSPs: one operating the CT domain and one using the companding technique. The former operates only on level-crossing samples; the proposed methodology shows a potential for high-quality outputs by using a complex interpolation function. Finally, a companding DSP is presented for MPEG audio. Companding DSPs adapt their dynamic range to the amplitude of their input; the resulting can offer high-quality outputs even for small inputs. By applying companding to MPEG DSPs, it is shown how the DSP distortion can be made almost inaudible, without requiring complex arithmetic hardware

Energy-Efficient Time-Based Encoders and Digital Signal Processors in Continuous Time

Continuous-time (CT) data conversion and continuous-time digital signal processing (DSP) are an interesting alternative to conventional methods of signal conversion and processing. This alternative proposes time-based encoding that may not suffer from aliasing; shows superior spectral properties (e.g. no quantization noise floor); and enables time-based, event-driven, flexible signal processing using digital circuits, thus scaling well with technology. Despite these interesting features, this approach has so far been limited by the CT encoder, due to both its relatively poor energy efficiency and the constraints it imposes on the subsequent CT DSP. In this thesis, we present three principles that address these limitations and help improve the CT ADC/DSP system. First, an adaptive-resolution encoding scheme that achieves first-order reconstruction with simple circuitry is proposed. It is shown that for certain signals, the scheme can significantly reduce the number of samples generated per unit of time for a given accuracy compared to schemes based on zero-order-hold reconstruction, thus promising to lead to low dynamic power dissipation at the system level. Presented next is a novel time-based CT ADC architecture, and associated encoding scheme, that allows a compact, energy-efficient circuit implementation, and achieves first-order quantization error spectral shaping. The design of a test chip, implemented in a 0.65-V 28-nm FDSOI process, that includes this CT ADC and a 10-tap programmable FIR CT DSP to process its output is described. The system achieves 32 dB – 42 dB SNDR over a 10 MHz – 50 MHz bandwidth, occupies 0.093 mm2, and dissipates 15 µW–163 µW as the input amplitude goes from zero to full scale. Finally, an investigation into the possibility of CT encoding using voltage-controlled oscillators is undertaken, and it leads to a CT ADC/DSP system architecture composed primarily of asynchronous digital delays. The latter makes the system highly digital and technology-scaling-friendly and, hence, is particularly attractive from the point of view of technology migration. The design of a test chip, where this delay-based CT ADC/DSP system architecture is used to implement a 16-tap programmable FIR filter, in a 1.2-V 28-nm FDSOI process, is described. Simulations show that the system will achieve a 33 dB – 40 dB SNDR over a 600 MHz bandwidth, while dissipating 4 mW

Stimulus generation technique for code simulation of FPGA based gamma spectroscopy system

The aim of this study is to develop a software that can systematically generate stimulus required for code simulation (functional and timing) of new digital processors in gamma spectroscopy system. Software must be able to produce stimulus that emulate ADC data of charge sensitive amplifier (CSA) output signal. Signal parameters such as pulse shape, amplitude, pulse width and count rate should be adjustable while allowing options such as pulse pile-up and random pulse events. To fulfill this objective, a pulse generator software PulseGEN has been developed. The software GUI is designed to operate in two modes, Single/Pile-Up Mode and Continuous Random Mode. Its ADC module simulates real-time ADC sampling. The output can be saved as input stimulus to test various functions of digital processors such as pulse height measurements, pile-up detection and correction, as well as random pulse detection and measurement that is similar to the actual real-time measurement. PulseGEN results have been compared and verified against commercial charge sensitive amplifier with NaI detector and NIM pulser

Optimal and Permissible Sampling Rates for First-Order Sampling of Two-Band Signals

Sampling theory plays an essential role in the advancement of digital signal processing (DSP). All known DSP processors only work with digital samples of an analog signal (continuous-time signal). Therefore, reliable sampling of a signal is crucial for the successive phases of DSP. A well-known industry standard for sufficient sampling of an analog signal is that the sampling rate is at least twice the highest frequency of the signal. Obviously, the greater the highest frequency of the signal, the higher the sampling rate required, hence, more wear and tear on the sampling device. This research focuses on developing sampling methods for passband signals, which arises for broad-band signal processing, and it has drawn great interests in the DSP community. A first-order sampling method with optimal and total identification of all permissible sampling rates for two-band passband signals is studied in this work. A rigorous proof for all the sampling rates is presented. It is shown that the new sampling rates are much lower than the industrial standard. Therefore, the new sampling mechanism has sound theoretical and commercial values. Quantitative analysis is performed on the proposed sampling method, including a fast algorithm for computing all feasible sampling rates for two-band passband signals

Digital implementation of the cellular sensor-computers

Two different kinds of cellular sensor-processor architectures are used nowadays in various applications. The first is the traditional sensor-processor architecture, where the sensor and the processor arrays are mapped into each other. The second is the foveal architecture, in which a small active fovea is navigating in a large sensor array. This second architecture is introduced and compared here. Both of these architectures can be implemented with analog and digital processor arrays. The efficiency of the different implementation types, depending on the used CMOS technology, is analyzed. It turned out, that the finer the technology is, the better to use digital implementation rather than analog

Principles of Neuromorphic Photonics

In an age overrun with information, the ability to process reams of data has become crucial. The demand for data will continue to grow as smart gadgets multiply and become increasingly integrated into our daily lives. Next-generation industries in artificial intelligence services and high-performance computing are so far supported by microelectronic platforms. These data-intensive enterprises rely on continual improvements in hardware. Their prospects are running up against a stark reality: conventional one-size-fits-all solutions offered by digital electronics can no longer satisfy this need, as Moore's law (exponential hardware scaling), interconnection density, and the von Neumann architecture reach their limits. With its superior speed and reconfigurability, analog photonics can provide some relief to these problems; however, complex applications of analog photonics have remained largely unexplored due to the absence of a robust photonic integration industry. Recently, the landscape for commercially-manufacturable photonic chips has been changing rapidly and now promises to achieve economies of scale previously enjoyed solely by microelectronics. The scientific community has set out to build bridges between the domains of photonic device physics and neural networks, giving rise to the field of \emph{neuromorphic photonics}. This article reviews the recent progress in integrated neuromorphic photonics. We provide an overview of neuromorphic computing, discuss the associated technology (microelectronic and photonic) platforms and compare their metric performance. We discuss photonic neural network approaches and challenges for integrated neuromorphic photonic processors while providing an in-depth description of photonic neurons and a candidate interconnection architecture. We conclude with a future outlook of neuro-inspired photonic processing.Comment: 28 pages, 19 figure

Configurable 3D-integrated focal-plane sensor-processor array architecture

A mixed-signal Cellular Visual Microprocessor architecture with digital processors is described. An ASIC implementation is also demonstrated. The architecture is composed of a regular sensor readout circuit array, prepared for 3D face-to-face type integration, and one or several cascaded array of mainly identical (SIMD) processing elements. The individual array elements derived from the same general HDL description and could be of different in size, aspect ratio, and computing resources

A user configurable data acquisition and signal processing system for high-rate, high channel count applications

Real-time signal processing in plasma fusion experiments is required for control and for data reduction as plasma pulse times grow longer. The development time and cost for these high-rate, multichannel signal processing systems can be significant. This paper proposes a new digital signal processing (DSP) platform for the data acquisition system that will allow users to easily customize real-time signal processing systems to meet their individual requirements. The D-TACQ reconfigurable user in-line DSP (DRUID) system carries out the signal processing tasks in hardware co-processors (CPs) implemented in an FPGA, with an embedded microprocessor (μP) for control. In the fully developed platform, users will be able to choose co-processors from a library and configure programmable parameters through the μP to meet their requirements. The DRUID system is implemented on a Spartan 6 FPGA, on the new rear transition module (RTM-T), a field upgrade to existing D-TACQ digitizers. As proof of concept, a multiply-accumulate (MAC) co-processor has been developed, which can be configured as a digital chopper-integrator for long pulse magnetic fusion devices. The DRUID platform allows users to set options for the integrator, such as the number of masking samples. Results from the digital integrator are presented for a data acquisition system with 96 channels simultaneously acquiring data at 500 kSamples/s per channel