An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

Wireless wire - ultra-low-power and high-data-rate wireless communication systems

With the rapid development of communication technologies, wireless personal-area communication systems gain momentum and become increasingly important. When the market gets gradually saturated and the technology becomes much more mature, new demands on higher throughput push the wireless communication further into the high-frequency and high-data-rate direction. For example, in the IEEE 802.15.3c standard, a 60-GHz physical layer is specified, which occupies the unlicensed 57 to 64 GHz band and supports gigabit links for applications such as wireless downloading and data streaming. Along with the progress, however, both wireless protocols and physical systems and devices start to become very complex. Due to the limited cut-off frequency of the technology and high parasitic and noise levels at high frequency bands, the power consumption of these systems, especially of the RF front-ends, increases significantly. The reason behind this is that RF performance does not scale with technology at the same rate as digital baseband circuits. Based on the challenges encountered, the wireless-wire system is proposed for the millimeter wave high-data-rate communication. In this system, beamsteering directional communication front-ends are used, which confine the RF power within a narrow beam and increase the level of the equivalent isotropic radiation power by a factor equal to the number of antenna elements. Since extra gain is obtained from the antenna beamsteering, less front-end gain is required, which will reduce the power consumption accordingly. Besides, the narrow beam also reduces the interference level to other nodes. In order to minimize the system average power consumption, an ultra-low power asynchronous duty-cycled wake-up receiver is added to listen to the channel and control the communication modes. The main receiver is switched on by the wake-up receiver only when the communication is identified while in other cases it will always be in sleep mode with virtually no power consumed. Before transmitting the payload, the event-triggered transmitter will send a wake-up beacon to the wake-up receiver. As long as the wake-up beacon is longer than one cycle of the wake-up receiver, it can be captured and identified. Furthermore, by adopting a frequency-sweeping injection locking oscillator, the wake-up receiver is able to achieve good sensitivity, low latency and wide bandwidth simultaneously. In this way, high-data-rate communication can be achieved with ultra-low average power consumption. System power optimization is achieved by optimizing the antenna number, data rate, modulation scheme, transceiver architecture, and transceiver circuitries with regards to particular application scenarios. Cross-layer power optimization is performed as well. In order to verify the most critical elements of this new approach, a W-band injection-locked oscillator and the wake-up receiver have been designed and implemented in standard TSMC 65-nm CMOS technology. It can be seen from the measurement results that the wake-up receiver is able to achieve about -60 dBm sensitivity, 10 mW peak power consumption and 8.5 µs worst-case latency simultaneously. When applying a duty-cycling scheme, the average power of the wake-up receiver becomes lower than 10 µW if the event frequency is 1000 times/day, which matches battery-based or energy harvesting-based wireless applications. A 4-path phased-array main receiver is simulated working with 1 Gbps data rate and on-off-keying modulation. The average power consumption is 10 µW with 10 Gb communication data per day

LOW-POWER FREQUENCY SYNTHESIS BASED ON INJECTION LOCKING

Ph.DDOCTOR OF PHILOSOPH

A Sub-Centimeter Ranging Precision LIDAR Sensor Prototype Based on ILO-TDC

This thesis introduces a high-resolution light detection and ranging (LIDAR) sensor system-on-a-chip (SoC) that performs sub-centimeter ranging precision and maximally 124-meter ranging distance. With off-chip connected avalanche photodiodes (APDs), the time-of-flight (ToF) are resolved through 31×1 time-correlated single photon counting (TCSPC) channels. Embedded time-to-digital converters (TDCs) support 52-ps time resolution and 14-bit dynamic range. A novel injection-locked oscillator (ILO) based TDC are proposed to minimize the power of fine TDC clock distribution, and improve time precision. The global PVT variation among ILO clock distribution is calibrated by an on-chip phase-looked-loop (PLL) that assures a reliable counting performance over wide operating range. The proposed LIDAR sensor is designed, fabricated, and tested in the 65nm CMOS technology. Whole SoC consumes 37mW and each TDC channel consumes 788μW at nominal operation. The proposed TDC design achieved single-shot precision of 38.5 ps, channel uniformity of 14 ps, and DNL/INL of 0.56/1.56 LSB, respectively. The performance of proposed ILO-TDC makes it an excellent candidate for global counting TCSPC in automotive LIDAR

High Performance Local Oscillator Design for Next Generation Wireless Communication

Local Oscillator (LO) is an essential building block in modern wireless radios. In modern wireless radios, LO often serves as a reference of the carrier signal to modulate or demod- ulate the outgoing or incoming data. The LO signal should be a clean and stable source, such that the frequency or timing information of the carrier reference can be well-defined. However, as radio architecture evolves, the importance of LO path design has become much more important than before. Of late, many radio architecture innovations have exploited sophisticated LO generation schemes to meet the ever-increasing demands of wireless radio performances. The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication. The thesis begins with a brief introduction of the aforementioned challenges followed by a discussion of the opportunities projected to overcome these challenges. To address the challenge of congested spectrum at frequency below 5GHz, novel ra- dio architectures such as cognitive radio, software-defined radio, and full-duplex radio have drawn significant research interest. Cognitive radio is a radio architecture that opportunisti- cally utilize the unused spectrum in an environment to maximize spectrum usage efficiency. Energy-efficient spectrum sensing is the key to implementing cognitive radio. To enable energy-efficient spectrum sensing, a fast-hopping frequency synthesizer is an essential build- ing block to swiftly sweep the carrier frequency of the radio across the available spectrum. Chapter 2 of this thesis further highlights the challenges and trade-offs of the current LO gen- eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation. To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept. In shifting from RF to mm-wave frequencies, the performance of wireless communication links is boosted by significant bandwidth and data-rate expansion. However, the demand for data-rate improvement is out-pacing the innovation of radio architectures. A >10Gb/s mm-wave wireless communication at 60GHz is required by emerging applications such as virtual-reality (VR) headsets, inter-rack data transmission at data center, and Ultra-High- Definition (UHD) TV home entertainment systems. Channel-bonding is considered to be a promising technique for achieving >10Gb/s wireless communication at 60GHz. Chapter 5 discusses the fundamental radio implementation challenges associated with channel-bonding for 60GHz wireless communication and the pros and cons of prior arts that attempted to address these challenges. It is followed by a discussion of the proposed 60GHz channel- bonding receiver, which utilizes only a single PLL and enables both contiguous and non- contiguous channel-bonding schemes. Finally, Chapter 6 presents the conclusion of this thesis

Récepteur Sans-Fil à Basse Consommation et à Modulation Mixte FSK-ASK pour les Dispositifs Médicaux

RÉSUMÉ Les émetteurs-récepteurs radiofréquences (RF) offrent le lien de communications le plus commun afin de mettre au point des dispositifs médicaux implantables dédiés aux interfaces homme-machines. La surveillance en continu des paramètres biologiques des patients nécessite un module de communication sans-fil capable de garantir un échange de données rapide, en temps réel, à faible puissance tout en étant implémenté dans un espace physique réduit. La consommation de puissance des dispositifs implantables joue un rôle important dans les durées de vie des batteries qui nécessitent une chirurgie pour leur remplacement, à moins qu’une technique de transfert de puissance sans-fil soit utilisée pour recharger la batterie ou alimenter l’implant a travers les tissus humains. Dans ce projet, nous avons conçu, implémenté et testé un récepteur RF à faible puissance et haut-débit de données opérant entre 902 et 928 MHz qui est la bande industrielle-scientifiquemédicale (Industrial, Scientific and Medical) d’Amérique du Nord. Ce récepteur fait partie d’un système de communication bidirectionnel dédié à l’interface sans-fil des dispositifs électroniques implantables et bénéficie d’une nouvelle technique de conversion de modulation par déplacement de fréquence (FSK) en Modulation par déplacement d’amplitude (ASK). Toutes les phases de conception et d’implémentation de la topologie adoptée pour les récepteurs RF sont survolées et discutées dans cette thèse. Les différents étages de circuits sont conçus selon une étude analytique fondée de la modulation FSK et ASK utilisées, ce qui permettra une amélioration des performances notamment le débit de transmission des données et la consommation de puissance. Tous les circuits sont réalisés de façon à ce que la consommation totale et la surface de silicium à réserver soient le minimum possible. Un oscillateur avec verrouillage par injection (Injection-Looked Oscillator - ILO) de faible puissance est réalisé pour assurer la conversion des signaux ASK en FSK. Une combinaison des avantages des deux architectures de modulation d’amplitude et de fréquence, pour les circuits d’émetteurrécepteur sans fil, a été réalisé avec le système proposé. Un module incluant un récepteur de réveil (Wake up) est ajouté afin d’optimiser la consommation totale du circuit en mettant tous les blocs à l’arrêt. Nous avons réalisé un récepteur de réveil RF compact et à faible coût, permettant de très faible niveaux de consommation d’énergie, une bonne sensibilité et une meilleure tolérance aux interférences. Le design est basé sur une topologie homodyne à détection d’enveloppe permettant une transposition directe du signal RF modulé en amplitude en un signal en bande de base. Cette architecture nécessite une architecture peu encombrante à intégrer qui élimine le problème des fréquences image pour la même topologie avec une modulation de fréquence.---------- ABSTRACT ISM band transceiver using a wake-up bloc for wireless body area networks (WBANs) wearable and implantable medical devices is proposed. The system achieves exceptionally low-power consumption and allows a high-data rate by combining the advantages of Frequency-Shift-Keying (FSK) and Amplitude-Shift- Keying (ASK) modulation techniques. The transceiver employs FSK modulation at a data rate of 8 Mbit/s to establish RF link among the medical device and a control unit. Transmitter (Tx) includes a new efficient FSK modulation scheme which offer up to 20 Mb/s of data-rate and dissipates around 0.084 nJ/b. The design of the proposed oscillator achieves variable frequency from 300 kHz to 8 MHz by adjusting the transistors geometry, the on-chip control signal and the tuning capacitors. In the transmitter path, the high-quality LOs Inand Quadrature-phase (I and Q) outputs are produced using a very low-power fully integrated integer-N frequency synthesizer. The architecture of the receiver is inspired from the super-regenerative receiver (SRR) topology which can be used to design a transceiver that is suitable for ASK modulation. In fact, this architecture is based mainly on envelope detection scheme which remove the need to process the carrier phase to reduce the complexity of integrated design. It has been shown too, that the envelope detection scheme is more robust to phase noise than the coherent scheme. The integrated receiver uses on a new FSK-to-ASK conversion technique. The conversion feature that we adopt in the main receiver design is based on the fact that the incident frequency of converter could be differentiated by the amplitude of output signal, which conducts to the frequency-to-amplitude conversion. Thanks to the injection locking oscillator (ILO). the new design of converter is located between the LNA as first part and the envelope detector as second part to benefit from the injection-locking isolation. On-Off-keying (OOK) fully passive wake-up circuit (WuRx) with energy harvesting from Radio Frequency (RF) link is used to optimize the power issipation of the RF transceiver in order to meet the low power requirement. The WuRx operates at the ISM 902–928 MHz. A high efficiency differential rectifier behaves as voltage multiplier. It generates the envelope of the input signal and provides the supply voltage for the rest of blocks including a low-power comparator and reference generators

Design of Frequency divider with voltage vontrolled oscillator for 60 GHz low power phase-locked loops in 65 nm RF CMOS

Increasing memory capacity in mobile devices, is driving the need of high-data rates equipment. The 7 GHz band around 60 GHz provides the opportunity for multi-gigabit/sec wireless communication. It is a real opportunity for developing next generation of High-Definition (HD) devices. In the last two decades there was a great proliferation of Voltage Controlled Oscillator (VCO) and Frequency Divider (FD) topologies in RF ICs on silicon, but reaching high performance VCOs and FDs operating at 60 GHz is in today's technology a great challenge. A key reason is the inaccuracy of CMOS active and passive device models at mm-W. Three critical issues still constitute research objectives at 60 GHz in CMOS: generation of the Local Oscillator (LO) signal (1), division of the LO signal for the Phase-Locked Loop (PLL) closed loop (2) and distribution of the LO signal (3). In this Thesis, all those three critical issues are addressed and experimentally faced-up: a divide-by-2 FD for a PLL of a direct-conversion transceiver operating at mm-W frequencies in 65 nm RF CMOS technology has been designed. Critical issues such as Process, Voltage and Temperature (PVT) variations, Electromagnetic (EM) simulations and power consumption are addressed to select and design a FD with high frequency dividing range. A 60 GHz VCO is co-designed and integrated in the same die, in order to provide the FD with mm-W input signal. VCOs and FDs play critical roles in the PLL. Both of them constitute the PLL core components and they would need co-design, having a big impact in the overall performance especially because they work at the highest frequency in the PLL. Injection Locking FD (ILFD) has been chosen as the optimum FD topology to be inserted in the control loop of mm-W PLL for direct-conversion transceiver, due to the high speed requirements and the power consumption constraint. The drawback of such topology is the limited bandwidth, resulting in narrow Locking Range (LR) for WirelessHDTM applications considering the impact of PVT variations. A simulation methodology is presented in order to analyze the ILFD locking state, proposing a first divide-by-2 ILFD design with continuous tuning. In order to design a wide LR, low power consumption ILFD, the impacts of various alternatives of low/high Q tank and injection scheme are deeply analysed, since the ILFD locking range depends on the Q of the tank and injection efficiency. The proposed 3-bit dual-mixing 60 GHz divide-by-2 LC-ILFD is designed with an accumulation of switching varactors binary scaled to compensate PVT variations. It is integrated in the same die with a 4-bit 60 GHz LC-VCO. The overall circuit is designed to allow measurements of the singles blocks stand-alone and working together. The co-layout is carried on with the EM modelling process of passives devices, parasitics and transmission lines extracted from the layout. The inductors models provided by the foundry are qualified up to 40 GHz, therefore the EM analysis is a must for post-layout simulation. The PVT variations have been simulated before manufacturing and, based on the results achieved, a PLL scheme PVT robust, considering frequency calibration, has been patented. The test chip has been measured in the CEA-Leti (Grenoble) during a stay of one week. The operation principle and the optimization trade-offs among power consumption, and locking ranges of the final selected ILFD topology have been demonstrated. Even if the experimental results are not completely in agreement with the simulations, due to modelling error and inaccuracy, the proposed technique has been validated with post-measurement simulations. As demonstrated, the locking range of a low-power, discrete tuned divide-by-2 ILFD can be enhanced by increasing the injection efficiency, without the drawbacks of higher power consumption and chip area. A 4-bits wide tuning range LC-VCO for mm-W applications has been co-designed using the selected 65 nm CMOS process.Postprint (published version

A robust 2.4 GHz time-of-arrival based ranging system with sub-meter accuracy: feasibility study and realization of low power CMOS receiver

Draadloze sensornetwerken worden meer en meer aangewend om verschillende soorten informatie te verzamelen. De locatie, waar deze informatie verzameld is, is een belangerijke eigenschap en voor sommige toepassingen, zoals het volgen van personen of goederen, zelfs de meest belangrijke en mogelijkmakende factor. Om de positie van een sensor te bepalen, is een technologie nodig die de afstand tot een gekend referentiepunt schat. Door verschillende afstandsmetingen te combineren, is het mogelijk de absolute locatie van de node te berekenen

Process and Temperature Compensated Wideband Injection Locked Frequency Dividers and their Application to Low-Power 2.4-GHz Frequency Synthesizers

There has been a dramatic increase in wireless awareness among the user community in the past five years. The 2.4-GHz Industrial, Scientific and Medical (ISM) band is being used for a diverse range of applications due to the following reasons. It is the only unlicensed band approved worldwide and it offers more bandwidth and supports higher data rates compared to the 915-MHz ISM band. The power consumption of devices utilizing the 2.4-GHz band is much lower compared to the 5.2-GHz ISM band. Protocols like Bluetooth and Zigbee that utilize the 2.4-GHz ISM band are becoming extremely popular. Bluetooth is an economic wireless solution for short range connectivity between PC, cell phones, PDAs, Laptops etc. The Zigbee protocol is a wireless technology that was developed as an open global standard to address the unique needs of low-cost, lowpower, wireless sensor networks. Wireless sensor networks are becoming ubiquitous, especially after the recent terrorist activities. Sensors are employed in strategic locations for real-time environmental monitoring, where they collect and transmit data frequently to a nearby terminal. The devices operating in this band are usually compact and battery powered. To enhance battery life and avoid the cumbersome task of battery replacement, the devices used should consume extremely low power. Also, to meet the growing demands cost and sized has to be kept low which mandates fully monolithic implementation using low cost process. CMOS process is extremely attractive for such applications because of its low cost and the possibility to integrate baseband and high frequency circuits on the same chip. A fully integrated solution is attractive for low power consumption as it avoids the need for power hungry drivers for driving off-chip components. The transceiver is often the most power hungry block in a wireless communication system. The frequency divider (prescaler) and the voltage controlled oscillator in the transmitter’s frequency synthesizer are among the major sources of power consumption. There have been a number of publications in the past few decades on low-power high-performance VCOs. Therefore this work focuses on prescalers. A class of analog frequency dividers called as Injection-Locked Frequency Dividers (ILFD) was introduced in the recent past as low power frequency division. ILFDs can consume an order of magnitude lower power when compared to conventional flip-flop based dividers. However the range of operation frequency also knows as the locking range is limited. ILFDs can be classified as LC based and Ring based. Though LC based are insensitive to process and temperature variation, they cannot be used for the 2.4-GHz ISM band because of the large size of on-chip inductors at these frequencies. This causes a lot of valuable chip area to be wasted. Ring based ILFDs are compact and provide a low power solution but are extremely sensitive to process and temperature variations. Process and temperature variation can cause ring based ILFD to loose lock in the desired operating band. The goal of this work is to make the ring based ILFDs useful for practical applications. Techniques to extend the locking range of the ILFDs are discussed. A novel and simple compensation technique is devised to compensate the ILFD and keep the locking range tight with process and temperature variations. The proposed ILFD is used in a 2.4-GHz frequency synthesizer that is optimized for fractional-N synthesis. Measurement results supporting the theory are provided

Design of Low-Power Short-Distance Transceiver for Wireless Sensor Networks

Ph.DDOCTOR OF PHILOSOPH