Thermal performance enhancement of packaging substrates with integrated vapor chamber

The first part of this research investigates the effects of copper structures, such as copper through-package-vias (TPVs), and copper traces in redistribution layer (RDL), on the thermal performance of glass interposers through numerical and experimental approaches. Numerical parametric study on 2.5D interposers shows that as more copper structures are incorporated in glass interposers, the performance of silicon and glass interposers becomes closer, showing 31% difference in thermal resistance, compared to 53% difference without any copper structures in both interposers. In the second part of this study, a thermal model of glass interposer mounted on the vapor chamber integrated PCB is developed using multi-scale modeling scheme. The comparison of thermal performance between silicon and glass interposers shows that integration of vapor chamber with PCB makes thermal performance of both interposers almost identical, overcoming the limitation posed by low thermal conductivity of glass. The third part of this thesis focuses on design, fabrication, and performance measurement of PCB integrated with vapor chamber. Copper micropillar wick structure is fabricated on PCB with electroplating process, and its wettability is enhanced by silica nanoparticle coating. Design of the wick for the vapor chamber is determined based on the capillary performance and permeability test results. Fabricated device with ultra-thin thickness (~800 µm) shows higher thermal performance than copper plated PCB with the same thickness. Finally, 3D computational fluid dynamics/heat transfer model of the vapor chamber is developed, and modeling result is compared with test result.Ph.D

Investigation of Cu‑Cu bonding for 2.5D and 3D system integration using self‑assembled monolayer as oxidation inhibitor

Das Cu-Cu-Bonden ist eine vielversprechende lötfreie Fine-Pitch-Verbindungstechnologie für die 2,5D- und 3D-Systemintegration. Diese Bondtechnologie wurde in den letzten Jahren intensiv untersucht und wird derzeit für miniaturisierte mikroelektronische Produkte eingesetzt. Allerdings, stellt das Cu‑Cu-Bonden zum einen sehr hohe Anforderungen an die Oberflächenplanarität und -reinheit, und zum anderen sollten die Bondpartner frei von Oxiden sein. Oxidiertes Cu erfordert erhöhte Bondparameter, um die Oxidschicht zu durchbrechen und zuverlässige Cu-Cu-Verbindungen zu erzielen. Diese Bondbedingungen sind für viele sensible Bauelemente nicht geeignet. Aus diesem Grund sollten alternative Technologien mit einer einfachen Technik zum Schutz von Cu vor Oxidation gefunden werden. In dieser Arbeit werden selbstorganisierte Monolagen (SAMs) für den Cu-Oxidationsschutz und die Verbesserung der Cu-Cu-Thermokompression- (TC) und Ultraschall- (US) Flip-Chip-Bondtechnologien untersucht. Die Experimente werden an Si-Chips mit galvanisch aufgebrachten Cu-Microbumps und Cu-Schichten durchgeführt. Die Arbeit beinhaltet die umfassende Charakterisierung der SAM für den Cu-Schutz, die Bewertung der technologischen Parameter für das TC- und US-Flip-Chip-Bonden sowie die Charakterisierung der Cu-Cu-Bondqualität (Scherfestigkeitstests, Bruchflächen- und Mikrostrukturanalysen). Eine Lagerung bei tiefen Temperaturen (bei ‑18 °C und ‑40 °C) bestätigte die langanhaltende Schutzwirkung der kurzkettigen SAMs für das galvanisch abgeschiedene Cu ohne chemisch-mechanische Politur. Der Einfluss der Tieftemperaturlagerung an Luft und der thermischen SAM-Desorption in einer Inertgasatmosphäre auf die TC-Verbindungsqualität wird im Detail analysiert. Die Idee, mit Hilfe der US-Leistung SAM mechanisch zu entfernen und gleichzeitig das US-Flip-Chip-Bonden zu starten, wurde in der Literatur bisher nicht systematisch untersucht. Die Methode ermöglicht kurze Bondzeiten, niedrige Bondtemperaturen und das Bonden an Umgebungsluft. Sowohl beim TC- als auch beim US-Flip-Chip-Bonden zeigt es sich, dass die Scherfestigkeit bei den Proben mit SAM-Passivierung um ca. 30 % höher ist als bei unbeschichteten Proben. Das Vorhandensein von Si- und Ti-Bruchflächen nach den Scherfestigkeitstests ist für die Proben mit der SAM-Passivierung typisch, was auf eine höhere Festigkeit solcher Verbindungen im Vergleich zu ungeschützten Proben schließen lässt. Die Transmissionselektronenmikroskopie (TEM) zeigt keine SAM-Spuren im zentralen Bereich der Cu-Cu-Grenzfläche nach dem US-Flip-Chip-Bonden. Die Ergebnisse dieser Arbeit zeigen die Verbesserung der Bondqualität durch den Einsatz von SAM zum Schutz des Cu vor Oxidation im Vergleich zum üblicherweise angewandten Cu-Vorätzen. Das gefundene technologische Prozessfenster für das US-Flip-Chip-Bonden an Luft bietet eine hohe Bondqualität bei 90 °C und 150 °C, bei 180 MPa, bei einer Bonddauer von 1 s an. Die in dieser Arbeit gewonnenen Erkenntnisse sind ein wichtiger Beitrag zum Verständnis des SAM-Einflusses auf Chips mit galvanischen Cu-Microbumps, bzw. Cu-Schichten, und zur weiteren Anwendung der Cu-Cu-Fine-Pitch-Bondtechnologie in der Mikroelektronik.Cu-Cu bonding is one of the most promising fine-pitch interconnect technologies with solder elimination for 2.5D and 3D system integration. This bonding technology has been intensively investigated in the last years and is currently in application for miniaturized microelectronics products. However, Cu-Cu bonding has very high demands on the sur-face planarity and purity, and the bonding partners should be oxide-free. Oxidized Cu requires elevated bonding parameters in order to break through the oxide layer and achieve reliable Cu-Cu interconnects. Those bonding conditions are undesirable for many devices (e.g. due to the temperature/pressure sensitivity). Therefore, alternative technologies with a simple technique for Cu protection from oxidation are required. Self-assembled monolayers (SAMs) are proposed for the Cu protection and the improvement of the Cu-Cu thermocompression (TC) and ultrasonic (US) flip-chip bonding technologies in this thesis. The experiments were carried out on Si dies with electroplated Cu microbumps and Cu layers. The thesis comprises the comprehensive characterization of the SAM for Cu protection, evaluation of technological parameters for TC and US flip-chip bonding as well as characterization of the Cu-Cu bonding quality (shear strength tests, fracture surface and microstructure analyses). The storage at low temperatures (at ‑18 °C and ‑40 °C) confirmed the prolonged protective effect of the short-chain SAMs for the electroplated Cu without chemical-mechanical polishing. The influence of the low-temperature storage in air and the thermal SAM desorption in an inert gas atmosphere on the TC bonding quality was analyzed in detail. The approach of using US power to mechanically remove SAM and simultaneously start the US flip-chip bonding has not been systematically investigated before. The method provides the benefit of short bonding time, low bonding temperature and bonding in ambient air. Both the TC and US flip-chip bonding results featured the shear strength that is approximately 30 % higher for the samples with SAM passivation in comparison to the uncoated samples. The presence of Si and Ti fracture surfaces after the shear strength tests is typical for the samples with the SAM passivation, which suggests a higher strength of such interconnects in comparison to the uncoated samples. The transmission electron microscopy (TEM) indicated no SAM traces at the central region of the Cu-Cu bonding interface after the US flip-chip bonding. The results of this thesis show the improvement of the bonding quality caused by the application of SAM for Cu protection from oxidation in comparison to the commonly applied Cu pre-treatments. The found technological process window for the US flip-chip bonding in air offers high bonding quality at 90 °C and 150 °C, at 180 MPa, for the bonding duration of 1 s. The knowledge gained in this thesis is an important contribution to the understanding of the SAM performance on chips with electroplated Cu microbumps/layers and further application of the Cu-Cu fine-pitch bonding technology for microelectronic devices

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra

異種ダイレット積層を用いたフレキシブルハイブリッドデバイスの集積技術に関する研究

Tohoku University福島誉史課

Microstructural and mechanical characteristics of micro-scale intermetallic compounds interconnections

Following the continually increasing demand for high-density interconnection and multilayer packaging for chips, solder bump size has decreased significantly over the years, this has led to some challenges in the reliability of interconnects. This thesis presents research into the resulting effects of miniaturization on the interconnection with Sn-solder, especially focusing on the full intermetallics (IMCs) micro-joints which appear in the 3D IC stacking packaging. Thereby, systematic studies have been conducted to study the microstructural evolution and reliability issues of Cu-Sn and Cu-Sn-Ni IMCs micro-joints. (1) Phenomenon of IMCs planar growth: The planar IMCs interlayer was asymmetric and composed of (Cu,Ni)6Sn5 mainly in Ni/Sn (2.5~5 µm)/Cu interconnect. Meanwhile, it was symmetric two-layer structure in Cu/Sn (2.5~5 µm)/Cu interconnect with the Cu3Sn fine grains underneath Cu6Sn5 cobblestone-shape-like grains for each IMCs layer. Besides, it is worth noticing that the appearance of Cu-rich whiskers (the mixture of Cu/Cu2O/SnOx/Cu6Sn5) could potentially lead to short-circuit in the cases of ultra-fine (<10 µm pitch) interconnects for the miniaturization of electronics devices. (2) Microstructural evolution process of Cu-Sn IMCs micro-joint: The simultaneous solidification of IMCs interlayer supressed the scalloped growth of Cu6Sn5 grains in Cu/Sn (2.5 µm)/Cu interconnect during the transient liquid phase (TLP) soldering process. The growth factor of Cu3Sn was in the range of 0.29~0.48 in Cu-Cu6Sn5 diffusion couple at 240~290 °C, which was impacted significantly by the type of substrates. And the subsequent homogenization process of Cu3Sn grains was found to be consistent with the description of flux-driven ripening (FDR) theory. Moreover, Kirkendall voids appeared only in the Cu3Sn layer adjacent to Cu-plated substrate, and this porous Cu3Sn micro-joint was mechanically robust during the shear test. (3) Microstructural evolution of Cu-Sn-Ni IMCs micro-joint: There was obvious inter-reaction between the interfacial reactions in Ni/Sn (1.5 µm)/Cu interconnect. The growth factor of (Cu,Ni)3Sn on Cu side was about 0.36 at 240 °C, and the reaction product on Ni side was changed from Ni3Sn4 into (Cu,Ni)6Sn5 with the increase of soldering temperature. In particular, the segregation of Ni atoms occurred along with phase transformation at 290 °C and thereby stabilized the (Cu,Ni)6Sn5 phase for the high Ni content of 20 at.%. (4) Micro-mechanical characteristics of Cu-Sn-Ni IMCs micro-joint: The Young s modulus and hardness of Cu-Sn-Ni IMCs were measured by nanoindentation test, such as 160.6±3.1 GPa/ 7.34±0.14 GPa for (Cu,Ni)6Sn5 and 183.7±4.0 GPa/ 7.38±0.46 GPa for (Cu,Ni)3Sn, respectively. Besides, in-situ nano-compression tests have been conducted on IMCs micro-cantilevers, the fracture strength turns out to be 2.46 GPa. And also, the ultimate tensile stress was calculated to be 2.3±0.7 GPa from in-situ micro-bending tests, which is not sensitive with the microstructural change of IMCs after dwelling at 290 °C

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Nanowires for 3d silicon interconnection – low temperature compliant nanowire-polymer film for z-axis interconnect

Semiconductor chip packaging has evolved from single chip packaging to 3D heterogeneous system integration using multichip stacking in a single module. One of the key challenges in 3D integration is the high density interconnects that need to be formed between the chips with through-silicon-vias (TSVs) and inter-chip interconnects. Anisotropic Conductive Film (ACF) technology is one of the low-temperature, fine-pitch interconnect method, which has been considered as a potential replacement for solder interconnects in line with continuous scaling of the interconnects in the IC industry. However, the conventional ACF materials are facing challenges to accommodate the reduced pad and pitch size due to the micro-size particles and the particle agglomeration issue. A new interconnect material - Nanowire Anisotropic Conductive Film (NW-ACF), composed of high density copper nanowires of ~ 200 nm diameter and 10-30 µm length that are vertically distributed in a polymeric template, is developed in this work to tackle the constrains of the conventional ACFs and serves as an inter-chip interconnect solution for potential three-dimensional (3D) applications

Contactless Test Access Mechanism for 3D IC

3D IC integration presents many advantages over the current 2D IC integration. It has the potential to reduce the power consumption and the physical size while supporting higher bandwidth and processing speed. Through Silicon Via’s (TSVs) are vertical interconnects between different layers of 3D ICs with a typical 5μm diameter and 50μm length. To test a 3D IC, an access mechanism is needed to apply test vectors to TSVs and observe their responses. However, TSVs are too small for access by current wafer probes and direct TSV probing may affect their physical integrity. In addition, the probe needles for direct TSV probing must be cleaned or replaced frequently. Contactless probing method resolves most of the TSV probing problems and can be employed for small-pitch TSVs. In this dissertation, contactless test access mechanisms for 3D IC have been explored using capacitive and inductive coupling techniques. Circuit models for capacitive and inductive communication links are extracted using 3D full-wave simulations and then circuit level simulations are carried out using Advanced Design System (ADS) design environment to verify the results. The effects of cross-talk and misalignment on the communication link have been investigated. A contactless TSV probing method using capacitive coupling is proposed and simulated. A prototype was fabricated using TSMC 65nm CMOS technology to verify the proposed method. The measurement results on the fabricated prototype show that this TSV probing scheme presents -55dB insertion loss at 1GHz frequency and maintains higher than 35dB signal-to-noise ratio within 5µm distance. A microscale contactless probe based on the principle of resonant inductive coupling has also been designed and simulated. Experimental measurements on a prototype fabricated in TSMC 65nm CMOS technology indicate that the data signal on the TSV can be reconstructed when the distance between the TSV and the probe remains less than 15µm

Hybrid microfluidic cooling and thermal isolation technologies for 3D ICs

A key challenge for three dimensional (3D) integrated circuits (ICs) is thermal management. There are two main thermal challenges in typical 3D ICs. First, in the homogeneous integration with multiple high-power tiers, an effective cooling solution that scales with the number of dice in the stack is needed. Second, in the heterogeneous integration, an effective thermal isolation solution is needed to ‘protect’ the low-power tier from the high-power tier. This research focuses to address these two thermal challenges through hybrid microfluidic cooling and thermal isolation technologies. Within-tier microfluidic cooling is proposed and demonstrated to cool a stack with multiple high-power tiers. Electrical thermal co-analysis is performed to understand the trade-offs between through silicon via (TSV) parasitics and heat sink performance. A TSV-compatible micropin-fin heat sink is designed, fabricated and thermally characterized in a single tier, and benchmarked with a conventional air-cooled heat sink. The designed heat sink has a thermal resistance of 0.269 K·cm2/W at a flow rate of 70 mL/min. High aspect ratios TSVs (18:1) are integrated in the micropin-fins. Within-tier microfluidic cooling is then implemented in 3D stacks to emulate different heating scenarios, such as memory-on-processor and processor-on-processor. Air gap and mechanically flexible interconnects (MFIs) are proposed for the first time to decrease the vertical thermal coupling between high-power (e.g. processor) and low-power tiers (e.g. memory or nanophotonics). A two-tier testbed with the proposed thermal isolation technology is designed, fabricated and tested. Compared with conventional 3D integration approach, thermal isolation technology helps reduce the temperature at a fixed location in the low-tier by 12.9 °C. The resistance of a single MFI is measured to be 46.49 mΩ.Ph.D