FPGA based technical solutions for high throughput data processing and encryption for 5G communication: A review

The field programmable gate array (FPGA) devices are ideal solutions for high-speed processing applications, given their flexibility, parallel processing capability, and power efficiency. In this review paper, at first, an overview of the key applications of FPGA-based platforms in 5G networks/systems is presented, exploiting the improved performances offered by such devices. FPGA-based implementations of cloud radio access network (C-RAN) accelerators, network function virtualization (NFV)-based network slicers, cognitive radio systems, and multiple input multiple output (MIMO) channel characterizers are the main considered applications that can benefit from the high processing rate, power efficiency and flexibility of FPGAs. Furthermore, the implementations of encryption/decryption algorithms by employing the Xilinx Zynq Ultrascale+MPSoC ZCU102 FPGA platform are discussed, and then we introduce our high-speed and lightweight implementation of the well-known AES-128 algorithm, developed on the same FPGA platform, and comparing it with similar solutions already published in the literature. The comparison results indicate that our AES-128 implementation enables efficient hardware usage for a given data-rate (up to 28.16 Gbit/s), resulting in higher efficiency (8.64 Mbps/slice) than other considered solutions. Finally, the applications of the ZCU102 platform for high-speed processing are explored, such as image and signal processing, visual recognition, and hardware resource management

Towards Viable Large Scale Heterogeneous Wireless Networks

We explore radio resource allocation and management issues related to a large-scale heterogeneous (hetnet) wireless system made up of several Radio Access Technologies (RATs) that collectively provide a unified wireless network to a diverse set of users through co-ordination managed by a centralized Global Resource Controller (GRC). We incorporate 3G cellular technologies HSPA and EVDO, 4G cellular technologies WiMAX and LTE, and WLAN technology Wi-Fi as the RATs in our hetnet wireless system. We assume that the user devices are either multi-modal or have one or more reconfigurable radios which makes it possible for each device to use any available RAT at any given time subject to resource-sharing agreements. For such a hetnet system where resource allocation is coordinated at a global level, characterizing the network performance in terms of various conflicting network efficiency objectives that takes costs associated with a network re-association operation into account largely remains an open problem. Also, all the studies to-date that try to characterize the network performance of a hetnet system do not account for RAT-specific implementation details and the management overhead associated with setting up a centralized control. We study the radio resource allocation problem and the implementation/management overhead issues associated with a hetnet system in two research phases. In the first phase, we develop cost models associated with network re-association in terms of increased power consumption and communication downtime taking into account various user device assumptions. Using these cost models in our problem formulations, the first phase focuses on resource allocation strategies where we use a high-level system modeling approach to study the achievable performance in terms of conflicting network efficiency measures of spectral efficiency, overall power consumption, and instantaneous and long-term fairness for each user in the hetnet system. Our main result from this phase of study suggests that the gain in spectral efficiency due to multi-access network diversity results in a tremendous increase in overall power consumption due to frequent re-associations required by user devices. We then develop a utility function-based optimization algorithm to characterize and achieve a desired tradeoff in terms of all four network efficiency measures of spectral efficiency, overall power consumption and instantaneous and long-term fairness. We show an increase in a multi-attribute system utility measure of up to 56.7% for our algorithm compared to other widely studied resource allocation algorithms including max-sum rate, proportional fairness, max-min fairness and min power. The second phase of our research study focuses on practical implementation issues including the overhead required to implement a centralized GRC solution in a hetnet system. Through detailed protocol level simulations performed in ns-2, we show an increase in spectral efficiency of up to 99% and an increase in instantaneous fairness of up to 28.5% for two sort-based user device-to-Access Point (AP)/Base Station (BS) association algorithms implemented at the GRC that aim to maximize system spectral efficiency and instantaneous fairness performance metrics respectively compared to a distributed solution where each user makes his/her own association decision. The efficiency increase for each respective attribute again results in a tremendous increase in power consumption of up to 650% and 794% for each respective algorithm implemented at the GRC compared to a distributed solution because of frequent re-associations

Partially reconfigurable SDR solution on FPGA

Abstract. Software-defined radios (SDR) have become more common in order to answer the increasing complexity of wireless communication standards. The flexibility offered by SDR technology in return makes it possible to create and implement even more complex standards so there exists a mutual evolution cycle. One of the technological opportunities pursued on SDR is changing the waveforms on the fly. The standards challenge the SDR development. Computing throughput needs to be high enough, the end product has to be energy efficient, and all of this must be accomplished as cheaply as possible. SDRs have a wide range of implementation opportunities from complete software designs to more hardware oriented with higher level software control. The extreme ends of these approaches suffer from energy dissipation and design cost issues, respectively. The compromises include application specific architectures and reconfigurable hardware. Solutions vary from software to hardware between cases and depending on the needs. This thesis concentrates on investigating partial reconfigurability on a field-programmable gate array (FPGA) in an SDR application. Based on the results, partial reconfigurability is an attractive mean to bolster SDR functionalities. Although the energy efficiency of the employed FPGA solution is inferior to using an application-specific integrated circuit (ASIC), the flexibility and cost of design set them apart. This study focuses on partial reconfiguration on Xilinx FPGA devices but it may show benefits for other devices that can utilize partial reconfiguration on their designs.Osittain uudelleenohjelmoitava ohjelmistoradio FPGA-piirillä. Tiivistelmä. Ohjelmistoradiot ovat yleistyneet entistä kehittyneempien langattomien kommunikointimenetelmien myötä ja tarpeesta vastata näiden vaatimuksiin. Samalla ohjelmistoradioiden joustavuus mahdollistaa uusien ja kompleksisempien standardien kehittämisen. Tätä voi pitää molemminpuolisena kehityssyklinä. Aaltomuotojen nopea vaihtaminen lennosta ohjelmistoradion ollessa käytössä on yksi kehityksen alla oleva teknologia. Kommunikointistandardit haastavat ohjelmistoradioiden kehityksen erilaisilla vaatimuksillaan. Esimerkiksi laskentatehon tulee olla korkea, lopputuotteen energiatehokas ja tämän tulee tapahtua mahdollisimman edullisesti. Ohjelmistoradioiden toteutukset vaihtelevat aina vahvoista ohjelmistopohjaisista arkkitehtuureista enemmän laitteistoon tukeutuviin versioihin. Ääripäissä tässä spektrissä ohjelmistoihin perustuvat toteutukset eivät ole riittävän energiatehokkaita ja laitteistoratkaisujen hinnat nousevat helposti korkealle. Keskitien ratkaisuja ovat sovelluskohtaiset arkkitehtuurit ja uudelleen ohjelmoitavat laitteistot. Implementaatiot vaihtelevat ohjelmisto-laitteisto skaalalla riippuen tarpeesta ja tilanteesta. Tämä opinnäytetyö keskittyy tutkimaan osittaista uudelleenohjelmoimista FPGA-piireillä ohjelmistoradion yhteydessä. Tulosten perusteella osittainen uudelleen ohjelmointi on houkutteleva tapa tehostaa ohjelmistoradioita. Vaikka FPGA-piirien energiatehokkuus ei ole yhtä hyvä kuin ASIC-toteutusten, niiden joustavuus ja suunnittelukustannukset ovat paremmat. Vaikka tämä työ keskittyy osittaiseen uudelleenohjelmointiin Xilinxin FPGA-piireillä, voi siitä olla hyötyä muissa tutkimuksissa ja laitteissa

Realizing Software Defined Radio - A Study in Designing Mobile Supercomputers.

The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a minimum. These implementations are time consuming to design and difficult to verify. A programmable hardware platform capable of supporting software implementations of the physical layer, or Software Defined Radio (SDR), has a number of advantages. These include support for multiple protocols, faster time-to-market, higher chip volumes, and support for late implementation changes. The challenge is to achieve this under the power budget of a mobile device. Wireless communications belong to an emerging class of applications with the processing requirements of a supercomputer but the power constraints of a mobile device -- mobile supercomputing. This thesis presents a set of design proposals for building a programmable wireless communication solution. In order to design a solution that can meet the lofty requirements of SDR, this thesis takes an application-centric design approach -- evaluate and optimize all aspects of the design based on the characteristics of wireless communication protocols. This includes a DSP processor architecture optimized for wireless baseband processing, wireless algorithm optimizations, and language and compilation tool support for the algorithm software and the processor hardware. This thesis first analyzes the software characteristics of SDR. Based on the analysis, this thesis proposes the Signal-Processing On-Demand Architecture (SODA), a fully programmable multi-core architecture that can support the computation requirements of third generation wireless protocols, while operating within the power budget of a mobile device. This thesis then presents wireless algorithm implementations and optimizations for the SODA processor architecture. A signal processing language extension (SPEX) is proposed to help the software development efforts of wireless communication protocols on SODA-like multi-core architecture. And finally, the SPIR compiler is proposed to automatically map SPEX code onto the multi-core processor hardware.Ph.D.Computer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/61760/1/linyz_1.pd

Novel Processing and Transmission Techniques Leveraging Edge Computing for Smart Health Systems

L'abstract è presente nell'allegato / the abstract is in the attachmen

Design Space Exploration and Resource Management of Multi/Many-Core Systems

The increasing demand of processing a higher number of applications and related data on computing platforms has resulted in reliance on multi-/many-core chips as they facilitate parallel processing. However, there is a desire for these platforms to be energy-efficient and reliable, and they need to perform secure computations for the interest of the whole community. This book provides perspectives on the aforementioned aspects from leading researchers in terms of state-of-the-art contributions and upcoming trends

Optimization of 5G Second Phase Heterogeneous Radio Access Networks with Small Cells

Due to the exponential increase in high data-demanding applications and their services per coverage area, it is becoming challenging for the existing cellular network to handle the massive sum of users with their demands. It is conceded to network operators that the current wireless network may not be capable to shelter future traffic demands. To overcome the challenges the operators are taking interest in efficiently deploying the heterogeneous network. Currently, 5G is in the commercialization phase. Network evolution with addition of small cells will develop the existing wireless network with its enriched capabilities and innovative features. Presently, the 5G global standardization has introduced the 5G New Radio (NR) under the 3rd Generation Partnership Project (3GPP). It can support a wide range of frequency bands (<6 GHz to 100 GHz). For different trends and verticals, 5G NR encounters, functional splitting and its cost evaluation are well-thought-out. The aspects of network slicing to the assessment of the business opportunities and allied standardization endeavours are illustrated. The study explores the carrier aggregation (Pico cellular) technique for 4G to bring high spectral efficiency with the support of small cell massification while benefiting from statistical multiplexing gain. One has been able to obtain values for the goodput considering CA in LTE-Sim (4G), of 40 Mbps for a cell radius of 500 m and of 29 Mbps for a cell radius of 50 m, which is 3 times higher than without CA scenario (2.6 GHz plus 3.5 GHz frequency bands). Heterogeneous networks have been under investigation for many years. Heterogeneous network can improve users service quality and resource utilization compared to homogeneous networks. Quality of service can be enhanced by putting the small cells (Femtocells or Picocells) inside the Microcells or Macrocells coverage area. Deploying indoor Femtocells for 5G inside the Macro cellular network can reduce the network cost. Some service providers have started their solutions for indoor users but there are still many challenges to be addressed. The 5G air-simulator is updated to deploy indoor Femto-cell with proposed assumptions with uniform distribution. For all the possible combinations of apartments side length and transmitter power, the maximum number of supported numbers surpassed the number of users by more than two times compared to papers mentioned in the literature. Within outdoor environments, this study also proposed small cells optimization by putting the Pico cells within a Macro cell to obtain low latency and high data rate with the statistical multiplexing gain of the associated users. Results are presented 5G NR functional split six and split seven, for three frequency bands (2.6 GHz, 3.5GHz and 5.62 GHz). Based on the analysis for shorter radius values, the best is to select the 2.6 GHz to achieve lower PLR and to support a higher number of users, with better goodput, and higher profit (for cell radius u to 400 m). In 4G, with CA, from the analysis of the economic trade-off with Picocell, the Enhanced multi-band scheduler EMBS provide higher revenue, compared to those without CA. It is clearly shown that the profit of CA is more than 4 times than in the without CA scenario. This means that the slight increase in the cost of CA gives back more than 4-time profit relatively to the ”without” CA scenario.Devido ao aumento exponencial de aplicações/serviços de elevado débito por unidade de área, torna-se bastante exigente, para a rede celular existente, lidar com a enormes quantidades de utilizadores e seus requisitos. É reconhecido que as redes móveis e sem fios atuais podem não conseguir suportar a procura de tráfego junto dos operadores. Para responder a estes desafios, os operadores estão-se a interessar pelo desenvolvimento de redes heterogéneas eficientes. Atualmente, a 5G está na fase de comercialização. A evolução destas redes concretizar-se-á com a introdução de pequenas células com aptidões melhoradas e características inovadoras. No presente, os organismos de normalização da 5G globais introduziram os Novos Rádios (NR) 5G no contexto do 3rd Generation Partnership Project (3GPP). A 5G pode suportar uma gama alargada de bandas de frequência (<6 a 100 GHz). Abordam-se as divisões funcionais e avaliam-se os seus custos para as diferentes tendências e verticais dos NR 5G. Ilustram-se desde os aspetos de particionamento funcional da rede à avaliação das oportunidades de negócio, aliadas aos esforços de normalização. Exploram-se as técnicas de agregação de espetro (do inglês, CA) para pico células, em 4G, a disponibilização de eficiência espetral, com o suporte da massificação de pequenas células, e o ganho de multiplexagem estatística associado. Obtiveram-se valores do débito binário útil, considerando CA no LTE-Sim (4G), de 40 e 29 Mb/s para células de raios 500 e 50 m, respetivamente, três vezes superiores em relação ao caso sem CA (bandas de 2.6 mais 3.5 GHz). Nas redes heterogéneas, alvo de investigação há vários anos, a qualidade de serviço e a utilização de recursos podem ser melhoradas colocando pequenas células (femto- ou pico-células) dentro da área de cobertura de micro- ou macro-células). O desenvolvimento de pequenas células 5G dentro da rede com macro-células pode reduzir os custos da rede. Alguns prestadores de serviços iniciaram as suas soluções para ambientes de interior, mas ainda existem muitos desafios a ser ultrapassados. Atualizou-se o 5G air simulator para representar a implantação de femto-células de interior com os pressupostos propostos e distribuição espacial uniforme. Para todas as combinações possíveis do comprimento lado do apartamento, o número máximo de utilizadores suportado ultrapassou o número de utilizadores suportado (na literatura) em mais de duas vezes. Em ambientes de exterior, propuseram-se pico-células no interior de macro-células, de forma a obter atraso extremo-a-extremo reduzido e taxa de transmissão dados elevada, resultante do ganho de multiplexagem estatística associado. Apresentam-se resultados para as divisões funcionais seis e sete dos NR 5G, para 2.6 GHz, 3.5GHz e 5.62 GHz. Para raios das células curtos, a melhor solução será selecionar a banda dos 2.6 GHz para alcançar PLR (do inglês, PLR) reduzido e suportar um maior número de utilizadores, com débito binário útil e lucro mais elevados (para raios das células até 400 m). Em 4G, com CA, da análise do equilíbrio custos-proveitos com pico-células, o escalonamento multi-banda EMBS (do inglês, Enhanced Multi-band Scheduler) disponibiliza proveitos superiores em comparação com o caso sem CA. Mostra-se claramente que lucro com CA é mais de quatro vezes superior do que no cenário sem CA, o que significa que um aumento ligeiro no custo com CA resulta num aumento de 4-vezes no lucro relativamente ao cenário sem CA

Cross-Layer Optimization for Power-Efficient and Robust Digital Circuits and Systems

With the increasing digital services demand, performance and power-efficiency become vital requirements for digital circuits and systems. However, the enabling CMOS technology scaling has been facing significant challenges of device uncertainties, such as process, voltage, and temperature variations. To ensure system reliability, worst-case corner assumptions are usually made in each design level. However, the over-pessimistic worst-case margin leads to unnecessary power waste and performance loss as high as 2.2x. Since optimizations are traditionally confined to each specific level, those safe margins can hardly be properly exploited. To tackle the challenge, it is therefore advised in this Ph.D. thesis to perform a cross-layer optimization for digital signal processing circuits and systems, to achieve a global balance of power consumption and output quality. To conclude, the traditional over-pessimistic worst-case approach leads to huge power waste. In contrast, the adaptive voltage scaling approach saves power (25% for the CORDIC application) by providing a just-needed supply voltage. The power saving is maximized (46% for CORDIC) when a more aggressive voltage over-scaling scheme is applied. These sparsely occurred circuit errors produced by aggressive voltage over-scaling are mitigated by higher level error resilient designs. For functions like FFT and CORDIC, smart error mitigation schemes were proposed to enhance reliability (soft-errors and timing-errors, respectively). Applications like Massive MIMO systems are robust against lower level errors, thanks to the intrinsically redundant antennas. This property makes it applicable to embrace digital hardware that trades quality for power savings.Comment: 190 page

Low-Power and Error-Resilient VLSI Circuits and Systems.

Efficient low-power operation is critically important for the success of the next-generation signal processing applications. Device and supply voltage have been continuously scaled to meet a more constrained power envelope, but scaling has created resiliency challenges, including increasing timing faults and soft errors. Our research aims at designing low-power and robust circuits and systems for signal processing by drawing circuit, architecture, and algorithm approaches. To gain an insight into the system faults due to supply voltage reduction, we researched the two primary effects that determine the minimum supply voltage (VMIN) in Intel’s tri-gate CMOS technology, namely process variations and gate-dielectric soft breakdown. We determined that voltage scaling increases the timing window that sequential circuits are vulnerable. Thus, we proposed a new hold-time violation metric to define hold-time VMIN, which has been adopted as a new design standard. Device scaling increases soft errors which affect circuit reliability. Through extensive soft error characterization using two 65nm CMOS test chips, we studied the soft error mechanisms and its dependence on supply voltage and clock frequency. This study laid the foundation of the first 65nm DSP chip design for a NASA spaceflight project. To mitigate such random errors, we proposed a new confidence-driven architecture that effectively enhances the error resiliency of deeply scaled CMOS and post-CMOS circuits. Designing low-power resilient systems can effectively leverage application-specific algorithmic approaches. To explore design opportunities in the algorithmic domain, we demonstrate an application-specific detection and decoding processor for multiple-input multiple-output (MIMO) wireless communication. To enhance the receive error rate for a robust wireless communication, we designed a joint detection and decoding technique by enclosing detection and decoding in an iterative loop to enhance both interference cancellation and error reduction. A proof-of-concept chip design was fabricated for the next-generation 4x4 256QAM MIMO systems. Through algorithm-architecture optimizations and low-power circuit techniques, our design achieves significant improvements in throughput, energy efficiency and error rate, paving the way for future developments in this area.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/110323/1/uchchen_1.pd

Dependable Embedded Systems

This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems