841 research outputs found

    Optimal MTCMOS reactivation under power supply noise and performance constraints

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    On-chip Voltage Regulator– Circuit Design and Automation

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    Title from PDF of title page viewed May 24, 2021Dissertation advisors: Masud H Chowdhury and Yugyung LeeVitaIncludes bibliographical references (page 106-121)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2021With the increase of density and complexity of high-performance integrated circuits and systems, including many-core chips and system-on-chip (SoC), it is becoming difficult to meet the power delivery and regulation requirements with off-chip regulators. The off-chip regulators become a less attractive choice because of the higher overheads and complexity imposed by the additional wires, pins, and pads. The increased I2R loss makes it challenging to maintain the integrity of different voltage domains under a lower supply voltage environment in the smaller technology nodes. Fully integrated on-chip voltage regulators have proven to be an effective solution to mitigate power delivery and integrity issues. Two types of regulators are considered as most promising for on-chip implementation: (i) the low-drop-out (LDO) regulator and (ii) the switched-capacitor (SC)regulator. The first part of our research mainly focused on the LDO regulator. Inspired by the recent surge of interest for cap-less voltage regulators, we presented two fully on-chip external capacitor-less low-dropout voltage regulator design. The second part of this proposal explores the complexity of designing each block of the regulator/analog circuit and proposed a design methodology for analog circuit synthesis using simulation and learning-based approach. As the complexity is increasing day-by-day in an analog circuit, hierarchical flow mostly uses for design automation. In this work, we focused mainly on Circuit-level, one of the significant steps in the flow. We presented a novel, efficient circuit synthesis flow based on simulation and learning-based optimization methods. The proposed methodology has two phases: the learning phase and the evaluation phase. Random forest, a supervised learning is used to reduce the sample points in the design space and iteration number during the learning phase. Additionally, symmetric constraints are used further to reduce the iteration number during the sizing process. We introduced a three-step circuit synthesis flow to automate the analog circuit design. We used H-spice as a simulation tool during the evaluation phase of the proposed methodology. The three most common analog circuits are chosen: single-stage differential amplifier, operational transconductance amplifier, and two-stage differential amplifier to verify the algorithm. The tool is developed in Python, and the technology we used is0.6um. We also verified the optimized result in Cadence Virtuoso.Introduction -- On-chip power delivery system -- Fundamentals of on-chip voltage regulator -- LDO design in 45NM technology -- LDO design in technology -- Analog design automation -- Proposed analog design methodology -- Energy efficient FDSOI and FINFET based power gating circuit using data retention transistor -- Conclusion and future wor

    Radar Sub-surface Sensing for Mapping the Extent of Hydraulic Fractures and for Monitoring Lake Ice and Design of Some Novel Antennas.

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    Hydraulic fracturing, which is a fast-developing well-stimulation technique, has greatly expanded oil and natural gas production in the United States. As the use of hydraulic fracturing has grown, concerns about its environmental impacts have also increased. A sub-surface imaging radar that can detect the extent of hydraulic fractures is highly demanded, but existing radar designs cannot meet the requirement of penetration range on the order of kilometers due to the exorbitant propagation loss in the ground. In the thesis, a medium frequency (MF) band sub-surface radar sensing system is proposed to extend the detectable range to kilometers in rock layers. Algorithms for cross-hole and single-hole configurations are developed based on simulations using point targets and realistic fractured rock models. A super-miniaturized borehole antenna and its feeding network are also designed for this radar system. Also application of imaging radars for sub-surface sensing frozen lakes at Arctic regions is investigated. The scattering mechanism is the key point to understand the radar data and to extract useful information. To explore this topic, a full-wave simulation model to analyze lake ice scattering phenomenology that includes columnar air bubbles is presented. Based on this model, the scattering mechanism from the rough ice/water interface and columnar air bubbles in the ice at C band is addressed and concludes that the roughness at the interface between ice and water is the dominate contributor to backscatter and once the lake is completely frozen the backscatter diminishes significantly. Radar remote sensing systems often require high-performance antennas with special specifications. Besides the borehole antenna for MF band subsurface imaging system, several other antennas are also designed for potential radar systems. Surface-to-borehole setup is an alternative configuration for subsurface imaging system, which requires a miniaturized planar antenna placed on the surface. Such antenna is developed with using artificial electromagnetic materials for size reduction. Furthermore, circularly polarized (CP) waveform can be used for imaging system and omnidirectional CP antenna is needed. Thus, a low-profile planar azimuthal omnidirectional CP antenna with gain of 1dB and bandwidth of 40MHz is designed at 2.4GHz by combining a novel slot antenna and a PIFA antenna.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/120674/1/wujf_1.pd

    Test and Diagnosis of Integrated Circuits

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    The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users, the manufacturing process is becoming finer and denser, making chips more prone to defects.The work presented in the HDR manuscript addresses the challenges of test and diagnosis of integrated circuits. It covers:- Power aware test;- Test of Low Power Devices;- Fault Diagnosis of digital circuits

    Circuit and System Level Design Optimization for Power Delivery And Management

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    As the VLSI technology scales to the nanometer scale, power consumption has become a critical design concern of VLSI circuits. Power gating and dynamic voltage and frequency scaling (DVFS) are two effective power management techniques that are widely utilized in modern chip designs. Various design challenges merge with these power management techniques in nanometer VLSI circuits. For example, power gating introduces unique power integrity issues and trade-offs between switching noise and rush current noise. Assuring power integrity and achieving power efficiency are two highly intertwined design challenges. In addition, these trade-offs significantly vary with the supply voltage. It is difficult to use conventional power-gated power delivery networks (PDNs) to fully meet the involved conflicting design constraints while maximizing power saving and minimizing supply noise. The DVFS controller and the DC-DC power converter are two highly intertwining enablers for DVFS-based systems. However, traditional DVFS techniques treat the design optimizations of the two as separate tasks, giving rise to sub-optimal designs. To address the above research challenges, we propose several circuit and system level design optimization techniques in this dissertation. For power-gated PDN designs, we propose systemic decoupling capacitor (decap) optimization strategies that optimally trade-off between power integrity and leakage saving. First, new global decap and re-routable decap design concepts are proposed to relax the tight interaction between power integrity and leakage power saving of power-gated PDN at a single supply voltage level. Furthermore, we propose to leverage re-routable decaps to provide flexible decap allocation structures to better suit multiple supply voltage levels. The proposed strategies are implemented in an automatic design flow for choosing optimal amount of local decaps, global decaps and re-routable decaps. The proposed techniques significantly increase leakage saving without jeopardizing power integrity. The flexible decap allocations enabled by re-routable decaps lead to optimal design trade-offs for PDNs operating with two supply voltage levels. To improve the effectiveness of DVFS, we analyze the drawbacks of circuit-level only and policy-level only optimizations and the promising opportunities resulted from the cross-layer co-optimization of the DC-DC converter and online learning based DVFS polices. We present a cross-layer approach that optimizes transition time, area, energy overhead of the DC-DC converter along with key parameters of an online learning DVFS controller. We systematically evaluate the benefits of the proposed co-optimization strategy based on several processor architectures, namely single and dual-core processors and processors with DVFS and power gating. Our results indicate that the co-optimization can introduce noticeable additional energy saving without significant performance degradation

    The ALICE TPC, a large 3-dimensional tracking device with fast readout for ultra-high multiplicity events

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    The design, construction, and commissioning of the ALICE Time-Projection Chamber (TPC) is described. It is the main device for pattern recognition, tracking, and identification of charged particles in the ALICE experiment at the CERN LHC. The TPC is cylindrical in shape with a volume close to 90 m^3 and is operated in a 0.5 T solenoidal magnetic field parallel to its axis. In this paper we describe in detail the design considerations for this detector for operation in the extreme multiplicity environment of central Pb--Pb collisions at LHC energy. The implementation of the resulting requirements into hardware (field cage, read-out chambers, electronics), infrastructure (gas and cooling system, laser-calibration system), and software led to many technical innovations which are described along with a presentation of all the major components of the detector, as currently realized. We also report on the performance achieved after completion of the first round of stand-alone calibration runs and demonstrate results close to those specified in the TPC Technical Design Report.Comment: 55 pages, 82 figure

    Development and application of fluorescence lifetime imaging and super-resolution microscopy

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    This PhD thesis reports the development and application of fluorescence imaging technologies for studying biological processes on spatial scales below the diffraction limit. Two strategies were addressed: firstly fluorescence lifetime imaging (FLIM) to study molecular processes, e.g. using Förster resonance energy transfer (FRET) to read out protein interactions, and secondly direct imaging of nanostructure using super-resolution microscopy (SRM). For quantitative FRET readouts, the development and characterisation of an automated multiwell plate FLIM microscope for high content analysis (HCA) is described. Open source software was developed for the data acquisition and analysis, and approaches to improve the performance of time-gated imaging for FLIM were evaluated including different methods to despeckle the laser illumination and testing of an enhanced detector. This instrument was evaluated using standard fluorescent dye samples and cells expressing fluorescent protein-based FRET constructs. It was applied to an assay of live cells expressing a FRET biosensor and to FRET readouts of aggregation of a membrane receptor (DDR1) in fixed cells. A novel instrument, combining structured illumination microscopy (SIM) with FLIM, was developed to explore the combination of SRM and FLIM-FRET readouts. This enabled the simultaneous mapping of molecular readouts with FLIM and super-resolved imaging. The SIM+FLIM system was applied to image collagen-stimulated DDR1 aggregation in cells, to image DNA structures during the cell cycle and to explore interactions between cell organelles. A novel SRM approach based on a stimulated emission of depletion (STED) microscope incorporating a spatial light modulator (SLM) was developed to provide straightforward robust alignment with collinear excitation/depletion beams, aberration correction, an extended field of view and multiple beam scanning for faster STED image acquisition. The performance of easySLM-STED was evaluated by imaging bead samples, labelled vimentin in Vero cells and the synaptonemal complex in homologs of C. elegans germlines.Open Acces
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