Circuit Modules for CMOS High-Power Short Pulse Generators

High-power short electrical pulses are important for high-performance functionality integration, such as the development of microelectromechanical/nanoelectromechanical systems (MEMS/NEMS), system on chip (SoC) and lab on chip (LoC). Many of these applications need high-power (low impedance load) short electrical pulses, in addition to CMOS digital intelligence. Therefore, it is of great interest to develop new circuit techniques to generate high-power high-voltage short electrical pulses on-chip. Results on pulse forming line (PFL) based CMOS pulse generator studies are reported. Through simulations, the effects of PFL length, switch speed and switch resistance on the output pulses are clarified. CMOS pulse generators are modeled and analyzed with on-chip transmission lines (TLs) as PFLs and CMOS transistors as switches. In the 0.13 um CMOS process with a 500 um long PFL, post layout simulations show that pulses of 10.4 ps width can be obtained. High-voltage and high-power outputs can be generated with other pulsed power circuits, such as Blumlein PFLs with stacked MOSFET switches. Thus, the PFL circuit significantly extends short and high-power pulse generation capabilities of CMOS technologies. A CMOS circuit with a 4 mm long PFL is implemented in the commercial 0.13 um technology. Pulses of ~ 160 ps duration and 110-200 mV amplitude on a 50 Ohms load are obtained when the power supply is tuned from 1.2 V to 2.0 V. Measurement Instruments limitations are probably the main reasons for the discrepancies among measurement and simulation results. A four-stage charge pump is presented as high voltage bias of the Blumlein PFLs pulse generator. Since Schottky diode has low forward drop voltage (~ 0.3V), using it as charge transfer cell can have high charge pumping gain and avoid additional control circuit for switch. A four-stage charge pump with Schottky diode as charge transfer cell is implemented in a commercial 0.13 um technology. Charge pump output and efficiency under different power supply voltages, load currents and clock frequencies are measured and presented. The maximum output voltage is ~ 6 V and the maximum efficiency is ~ 50%

Two-Phase DC-DC Buck Converter for Power Amplifier Modulation

This thesis presents the theory, design, layout and a proposal for measurement set up of a synchronous DC-DC buck converter. This converter will be used as the supply modulator of power amplifier of mobile phones. The design is done using 45nm CMOS technology. Pmos and nmos switches are synchronously turns on and off for DC voltage conversion. Second order LC type filter is used to filter out the ac component from output. Two phase interleaving is done to reduce the output ripple voltage. Pulse Width Modulation (PWM) method is used for generating the control signal. Several techniques like dead time control mechanism, reduced gate drive voltage for switches are applied for improving the efficiency of the converter. The operating voltage range of the converter is 3.3-4.2V and it can produce 0.5-3V output voltage with 2W of maximum output power. It has maximum load current of 700mA. The switching frequency of the converter can be varied from 10MHz to 100MHz. The ripple voltage is less than 10mV for 50MHz switching frequency. The converter shows good results in terms of power density and simulated efficiency which are 1.65W/mm2 and 88.5%

Millimeter-Wave Super-Regenerative Receivers for Wireless Communication and Radar

Today’s world is becoming increasingly automated and interconnected with billions of smart devices coming online, leading to a steep rise in energy consumption from small microelectronics. This coincides with an urgent push to transform global energy production to green energies, causing disruptions and energy shortages, and making the case for efficient energy use ever more pressing. Two major areas where high growth is expected are the fields of wireless communication and radar sensors. Millimeter-wave frequency bands are planned for fifth-generation (5G) and sixth-generation (6G) cellular communication standards, as well as automotive frequency-modulated continuous wave (FMCW) radar systems for driving assistance and automation. Fast silicon-based technologies enable these advances by operating at high maximum frequencies, such as the silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technologies. However, even the fastest transistors suffer from low and energy expensive gains at millimeter-wave frequencies. Rather than incremental improvements in circuit efficiency using conventional approaches, a disruptive revolution for green microelectronics could be enabled by exploring the low-power benefits of the super-regenerative receiver for some applications. The super-regenerative receiver uses a regenerative oscillator circuit to increase the gain by positive feedback, through coupling energy from the output back into the input. Careful bias and control of the circuit enables a very large gain from a small number of transistors and a very low energy dissipation. Thus, the super-regenerative oscillator could be used to replace amplifier circuits in high data rate wireless communication systems, or as active reflectors to increase the range of FMCW radar systems, greatly reducing the power consumption. The work in this thesis presents fundamental scientific research into the topic of energy-efficient millimeter-wave super-regenerative receivers for use in civilian wireless communication and radar applications. This research work covers the theory, analysis, and simulations, all the way up to the proof of concept, hardware realization, and experimental characterization. Analysis and modeling of regenerative oscillator circuits is presented and used to improve the understanding of the circuit operation, as well as design goals according to the specific application needs. Integrated circuits are investigated and characterized as a proof of concept for a high data rate wireless communication system operating between 140–220 GHz, and an automotive radar system operating at 60 GHz. Amplitude and phase regeneration capabilities for complex modulation are investigated, and principles for spectrum characterization are derived. The circuits are designed and fabricated in a 130 nm SiGe HBT technology, combining bipolar and complementary metal-oxide semiconductor (BiCMOS) transistors. To prove the feasibility of the research concepts, the work achieves a wireless communication link at 16 Gbit/s over 20 cm distance with quadrature amplitude modulation (QAM), which is a world record for the highest data rate ever reported in super-regenerative circuits. This was powered by a super-regenerative oscillator circuit operating at 180 GHz and providing 58 dB of gain. Energy efficiency is also considerably high, drawing 8.8 mW of dc power consumption, which corresponds to a highly efficient 0.6 pJ/bit. Packaging and module integration innovations were implemented for the system experiments, and additional broadband circuits were investigated to generate custom quench waveforms to further enhance the data rate. For radar active reflectors, a regenerative gain of 80 dB is achieved at 60 GHz from a single circuit, which is the best in its frequency range, despite a low dc power consumption of 25 mW

Design and Implementation of an Integrated Biosensor Platform for Lab-on-a-Chip Diabetic Care Systems

Recent advances in semiconductor processing and microfabrication techniques allow the implementation of complex microstructures in a single platform or lab on chip. These devices require fewer samples, allow lightweight implementation, and offer high sensitivities. However, the use of these microstructures place stringent performance constraints on sensor readout architecture. In glucose sensing for diabetic patients, portable handheld devices are common, and have demonstrated significant performance improvement over the last decade. Fluctuations in glucose levels with patient physiological conditions are highly unpredictable and glucose monitors often require complex control algorithms along with dynamic physiological data. Recent research has focused on long term implantation of the sensor system. Glucose sensors combined with sensor readout, insulin bolus control algorithm, and insulin infusion devices can function as an artificial pancreas. However, challenges remain in integrated glucose sensing which include degradation of electrode sensitivity at the microscale, integration of the electrodes with low power low noise readout electronics, and correlation of fluctuations in glucose levels with other physiological data. This work develops 1) a low power and compact glucose monitoring system and 2) a low power single chip solution for real time physiological feedback in an artificial pancreas system. First, glucose sensor sensitivity and robustness is improved using robust vertically aligned carbon nanofiber (VACNF) microelectrodes. Electrode architectures have been optimized, modeled and verified with physiologically relevant glucose levels. Second, novel potentiostat topologies based on a difference-differential common gate input pair transimpedance amplifier and low-power voltage controlled oscillators have been proposed, mathematically modeled and implemented in a 0.18μm [micrometer] complementary metal oxide semiconductor (CMOS) process. Potentiostat circuits are widely used as the readout electronics in enzymatic electrochemical sensors. The integrated potentiostat with VACNF microelectrodes achieves competitive performance at low power and requires reduced chip space. Third, a low power instrumentation solution consisting of a programmable charge amplifier, an analog feature extractor and a control algorithm has been proposed and implemented to enable continuous physiological data extraction of bowel sounds using a single chip. Abdominal sounds can aid correlation of meal events to glucose levels. The developed integrated sensing systems represent a significant advancement in artificial pancreas systems

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Innovative Concepts for the Electronic Interface of Massively Parallel MRI Phased Imaging Arrays

In Magnetic Resonance Imaging (MRI), the concept of parallel imaging shows significant enhancements in boosting the signal-to-noise ratio, reducing the imaging time, and enlarging the imaging field of view. However, this concept necessitates increased size, cost, and complexity of the MR system. This thesis introduces an innovative solution for the electronics of the MRI system that allows parallel imaging with massive number of channels while avoiding, at the same time, the associated drawback

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

A portable device for time-resolved fluorescence based on an array of CMOS SPADs with integrated microfluidics

[eng] Traditionally, molecular analysis is performed in laboratories equipped with desktop instruments operated by specialized technicians. This paradigm has been changing in recent decades, as biosensor technology has become as accurate as desktop instruments, providing results in much shorter periods and miniaturizing the instrumentation, moving the diagnostic tests gradually out of the central laboratory. However, despite the inherent advantages of time-resolved fluorescence spectroscopy applied to molecular diagnosis, it is only in the last decade that POC (Point Of Care) devices have begun to be developed based on the detection of fluorescence, due to the challenge of developing high-performance, portable and low-cost spectroscopic sensors. This thesis presents the development of a compact, robust and low-cost system for molecular diagnosis based on time-resolved fluorescence spectroscopy, which serves as a general-purpose platform for the optical detection of a variety of biomarkers, bridging the gap between the laboratory and the POC of the fluorescence lifetime based bioassays. In particular, two systems with different levels of integration have been developed that combine a one-dimensional array of SPAD (Single-Photon Avalanch Diode) pixels capable of detecting a single photon, with an interchangeable microfluidic cartridge used to insert the sample and a laser diode Pulsed low-cost UV as a source of excitation. The contact-oriented design of the binomial formed by the sensor and the microfluidic, together with the timed operation of the sensors, makes it possible to dispense with the use of lenses and filters. In turn, custom packaging of the sensor chip allows the microfluidic cartridge to be positioned directly on the sensor array without any alignment procedure. Both systems have been validated, determining the decomposition time of quantum dots in 20 nl of solution for different concentrations, emulating a molecular test in a POC device.[cat] Tradicionalment, l'anàlisi molecular es realitza en laboratoris equipats amb instruments de sobretaula operats per tècnics especialitzats. Aquest paradigma ha anat canviant en les últimes dècades, a mesura que la tecnologia de biosensor s'ha tornat tan precisa com els instruments de sobretaula, proporcionant resultats en períodes molt més curts de temps i miniaturitzant la instrumentació, permetent així, traslladar gradualment les proves de diagnòstic fora de laboratori central. No obstant això i malgrat els avantatges inherents de l'espectroscòpia de fluorescència resolta en el temps aplicada a la diagnosi molecular, no ha estat fins a l'última dècada que s'han començat a desenvolupar dispositius POC (Point Of Care) basats en la detecció de la fluorescència, degut al desafiament que suposa el desenvolupament de sensors espectroscòpics d'alt rendiment, portàtils i de baix cost. Aquesta tesi presenta el desenvolupament d'un sistema compacte, robust i de baix cost per al diagnòstic molecular basat en l'espectroscòpia de fluorescència resolta en el temps, que serveixi com a plataforma d'ús general per a la detecció òptica d'una varietat de biomarcadors, tancant la bretxa entre el laboratori i el POC dels bioassaigs basats en l'anàlisi de la pèrdua de la fluorescència. En particular, s'han desenvolupat dos sistemes amb diferents nivells d'integració que combinen una matriu unidimensional de píxels SPAD (Single-Photon Avalanch Diode) capaços de detectar un sol fotó, amb un cartutx microfluídic intercanviable emprat per inserir la mostra, així com un díode làser UV premut de baix cost com a font d'excitació. El disseny orientat a la detecció per contacte de l'binomi format pel sensor i la microfluídica, juntament amb l'operació temporitzada dels sensors, permet prescindir de l'ús de lents i filtres. Al seu torn, l'empaquetat a mida de l'xip sensor permet posicionar el cartutx microfluídic directament sobre la matriu de sensors sense cap procediment d'alineament. Tots dos sistemes han estat validats determinant el temps de descomposició de "quantum dots" en 20 nl de solució per a diferents concentracions, emulant així un assaig molecular en un dispositiu POC

Design of an 866 MHz On-chip Frequency Synthesizer

There is a strong need for stable frequency references with large tuning ranges in today\u27s communication systems. While the crystal oscillators assure good frequency stability, it is not possible to achieve a large frequency range by tuning the passive components attached to them. Frequency synthesizers are usually used for this purpose because of their ability to produce a variety of output frequencies. The Phase Locked Loop (PLL) based frequency synthesizer is the most preferred of all types of synthesizers available because of its additional features like programmability, low noise and low cost as well as high accuracy and stability. The main idea of this PLL-based synthesizer is to phase-lock its output signal with an input reference signal and to produce a synchronous output. It does this by generating an error signal to correct the oscillator frequency. This functionality is achieved by integrating a phase detector, charge pump, loop filter and voltage controlled oscillator block in series with a frequency divider in feedback. This thesis presents, in detail, the design of all the individual PLL blocks, the strategies employed in the design, issues faced in testing and the test data from simulation and measurement. All the above mentioned PLL blocks are designed in the 130 nm IBM-CMOS cmrf8sf process and optimized for low power consumption. PLLs are used in almost all kinds of communication systems, transmitters and receivers for applications such as carrier recovery, carrier generation, clock slew correction, frequency modulation and demodulation

Development of electronics for microultrasound capsule endoscopy

Development of intracorporeal devices has surged in the last decade due to advancements in the semiconductor industry, energy storage and low-power sensing systems. This work aims to present a thorough systematic overview and exploration of the microultrasound (µUS) capsule endoscopy (CE) field as the development of electronic components will be key to a successful applicable µUSCE device. The research focused on investigating and designing high-voltage (HV, < 36 V) generating and driving circuits as well as a low-noise amplifier (LNA) for battery-powered and volume-limited systems. In implantable applications, HV generation with maximum efficiency is required to improve the operational lifetime whilst reducing the cost of the device. A fully integrated hybrid (H) charge pump (CP) comprising a serial-parallel (SP) stage was designed and manufactured for > 20 V and 0 - 100 µA output capabilities. The results were compared to a Dickson (DKCP) occupying the same chip area; further improvements in the SPCP topology were explored and a new switching scheme for SPCPs was introduced. A second regulated CP version was excogitated and manufactured to use with an integrated µUS pulse generator. The CP was manufactured and tested at different output currents and capacitive loads; its operation with an US pulser was evaluated and a novel self-oscillating CP mechanism to eliminate the need of an auxiliary clock generator with a minimum area overhead was devised. A single-output universal US pulser was designed, manufactured and tested with 1.5 MHz, 3 MHz, and 28 MHz arrays to achieve a means of fully-integrated, low-power transducer driving. The circuit was evaluated for power consumption and pulse generation capabilities with different loads. Pulse-echo measurements were carried out and compared with those from a commercial US research system to characterise and understand the quality of the generated pulse. A second pulser version for a 28 MHz array was derived to allow control of individual elements. The work involved its optimisation methodology and design of a novel HV feedback-based level-shifter. A low-noise amplifier (LNA) was designed for a wide bandwidth µUS array with a centre frequency of 28 MHz. The LNA was based on an energy-efficient inverter architecture. The circuit encompassed a full power-down functionality and was investigated for a self-biased operation to achieve lower chip area. The explored concepts enable realisation of low power and high performance LNAs for µUS frequencies