Low phase noise, high bandwidth frequency synthesis techniques

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 243-249).A quantization noise reduction technique is proposed that allows fractional-N frequency synthesizers to achieve high closed loop bandwidth and low output phase noise simultaneously. Quantization induced phase noise is the bottleneck in state-of-the-art synthesizer design, and results in a noise-bandwidth tradeoff that typically limits closed loop synthesizer bandwidths to be <100kHz for adequate phase noise performance to be achieved. Using the proposed technique, quantization noise is reduced to the point where intrinsic noise sources (VCO, charge-pump, reference and PFD noise) ultimately limit noise performance. An analytical model that draws an analogy between fractional-N frequency synthesizers and MASH A digital-to-analog converters is proposed. Calculated performance of a synthesizer implementing the proposed quantization noise reduction techniques shows excellent agreement with simulation results of a behavioral model. Behavioral modeling techniques that progressively incorporate non-ideal circuit behavior based on SPICE level simulations are proposed. The critical circuits used to build the proposed synthesizer are presented.(cont.) These include a divider retiming circuit that avoids meta-stability related to synchronizing an asynchronous signal, a timing mismatch compensation block used by a dual divider path PFD, and a unit element current source design for reduced output phase noise. Measurement results of a prototype 0.18/m CMOS synthesizer show that quantization noise is suppressed by 29dB when the proposed synthesizer architecture is compared to 2nd order EA frequency synthesizer. The 1MHz closed loop bandwidth allows the synthesizer to be modulated by up to 1Mb/s GMSK data for use as a transmitter with 1.8GHz and 900MHz outputs. The analytical model is used to back extract on-chip mismatch parameters that are not directly measurable. This represents a new analysis technique that is useful in the characterization of fractional-N frequency synthesizers.by Scott Edward Meninger.Ph.D

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

Coherent population trapping resonances with linearly polarized light for all-optical miniature atomic clocks

We present a joint theoretical and experimental characterization of the coherent population trapping (CPT) resonance excited on the D1 line of 87Rb atoms by bichromatic linearly polarized laser light. We observe high-contrast transmission resonances (up to 25%), which makes this excitation scheme promising for miniature all-optical atomic clock applications. We also demonstrate cancellation of the first-order light shift by proper choice of the frequencies and relative intensities of the two laser field components. Our theoretical predictions are in good agreement with the experimental results.Comment: 8 pages, 7 figure

Long-distance frequency transfer over an urban fiber link using optical phase stabilization

We transferred the frequency of an ultra-stable laser over 86 km of urban fiber. The link is composed of two cascaded 43-km fibers connecting two laboratories, LNE-SYRTE and LPL in Paris area. In an effort to realistically demonstrate a link of 172 km without using spooled fiber extensions, we implemented a recirculation loop to double the length of the urban fiber link. The link is fed with a 1542-nm cavity stabilized fiber laser having a sub-Hz linewidth. The fiber-induced phase noise is measured and cancelled with an all fiber-based interferometer using commercial off the shelf pigtailed telecommunication components. The compensated link shows an Allan deviation of a few 10-16 at one second and a few 10-19 at 10,000 seconds

Architectures for RF Frequency synthesizers

Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.\ud Written for:\ud Electrical and electronic engineer

The Measurement of AM noise of Oscillators

The close-in AM noise is often neglected, under the assumption that it is a minor problem as compared to phase noise. With the progress of technology and of experimental science, this assumption is no longer true. Yet, information in the literature is scarce or absent. This report describes the measurement of the AM noise of rf/microwave sources in terms of Salpha(f), i.e., the power spectrum density of the fractional amplitude fluctuation alpha. The proposed schemes make use of commercial power detectors based on Schottky and tunnel diodes, in single-channel and correlation configuration. There follow the analysis of the front-end amplifier at the detector output, the analysis of the methods for the measurement of the power-detector noise, and a digression about the calibration procedures. The measurement methods are extended to the relative intensity noise (RIN) of optical beams, and to the AM noise of the rf/microwave modulation in photonic systems. Some rf/microwave synthesizers and oscillators have been measured, using correlation and moderate averaging. As an example, the flicker noise of a low-noise quartz oscillator (Wenzel 501-04623E) is Salpha = 1.15E-13/f, which is equivalent to an Allan deviation of sigma_alpha = 4E-7. The measurement systems described exhibit the world-record lowest background noise.Comment: 39 pages, 22 figures, 8 tables, 21 references, list of symbol

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Process and Temperature Compensated Wideband Injection Locked Frequency Dividers and their Application to Low-Power 2.4-GHz Frequency Synthesizers

There has been a dramatic increase in wireless awareness among the user community in the past five years. The 2.4-GHz Industrial, Scientific and Medical (ISM) band is being used for a diverse range of applications due to the following reasons. It is the only unlicensed band approved worldwide and it offers more bandwidth and supports higher data rates compared to the 915-MHz ISM band. The power consumption of devices utilizing the 2.4-GHz band is much lower compared to the 5.2-GHz ISM band. Protocols like Bluetooth and Zigbee that utilize the 2.4-GHz ISM band are becoming extremely popular. Bluetooth is an economic wireless solution for short range connectivity between PC, cell phones, PDAs, Laptops etc. The Zigbee protocol is a wireless technology that was developed as an open global standard to address the unique needs of low-cost, lowpower, wireless sensor networks. Wireless sensor networks are becoming ubiquitous, especially after the recent terrorist activities. Sensors are employed in strategic locations for real-time environmental monitoring, where they collect and transmit data frequently to a nearby terminal. The devices operating in this band are usually compact and battery powered. To enhance battery life and avoid the cumbersome task of battery replacement, the devices used should consume extremely low power. Also, to meet the growing demands cost and sized has to be kept low which mandates fully monolithic implementation using low cost process. CMOS process is extremely attractive for such applications because of its low cost and the possibility to integrate baseband and high frequency circuits on the same chip. A fully integrated solution is attractive for low power consumption as it avoids the need for power hungry drivers for driving off-chip components. The transceiver is often the most power hungry block in a wireless communication system. The frequency divider (prescaler) and the voltage controlled oscillator in the transmitter’s frequency synthesizer are among the major sources of power consumption. There have been a number of publications in the past few decades on low-power high-performance VCOs. Therefore this work focuses on prescalers. A class of analog frequency dividers called as Injection-Locked Frequency Dividers (ILFD) was introduced in the recent past as low power frequency division. ILFDs can consume an order of magnitude lower power when compared to conventional flip-flop based dividers. However the range of operation frequency also knows as the locking range is limited. ILFDs can be classified as LC based and Ring based. Though LC based are insensitive to process and temperature variation, they cannot be used for the 2.4-GHz ISM band because of the large size of on-chip inductors at these frequencies. This causes a lot of valuable chip area to be wasted. Ring based ILFDs are compact and provide a low power solution but are extremely sensitive to process and temperature variations. Process and temperature variation can cause ring based ILFD to loose lock in the desired operating band. The goal of this work is to make the ring based ILFDs useful for practical applications. Techniques to extend the locking range of the ILFDs are discussed. A novel and simple compensation technique is devised to compensate the ILFD and keep the locking range tight with process and temperature variations. The proposed ILFD is used in a 2.4-GHz frequency synthesizer that is optimized for fractional-N synthesis. Measurement results supporting the theory are provided

Integrated radio frequency synthetizers for wireless applications

This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed. The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance. The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.reviewe

Relationships Between the Performance of Time/Frequency Standards and Navigation/Communication Systems

The relationship between system performance and clock or oscillator performance is discussed. Tradeoffs discussed include: short term stability versus bandwidth requirements; frequency accuracy versus signal acquisition time; flicker of frequency and drift versus resynchronization time; frequency precision versus communications traffic volume; spectral purity versus bit error rate, and frequency standard stability versus frequency selection and adjustability. The benefits and tradeoffs of using precise frequency and time signals are various levels of precision and accuracy are emphasized