Combining SysML and AADL for the design, validation and implementation of critical systems

The realization of critical systems goes through multiple phases of specification, design, integration, validation, and testing. It starts from high-level sketches down to the final product. Model-Based Design has been acknowledged as a good conveyor to capture these steps. Yet, there is no universal solution to represent all activities. Two candidates are the OMG-based SysML to perform high-level modeling tasks, and the SAE AADL to perform lower-level ones, down to the implementation. The paper shares an experience on the seamless use of SysML and the AADL to model, validate/verify and implement a flight management system

CMOS circuit implementations for neuron models

The mathematical neuron basic cells used as basic cells in popular neural network architectures and algorithms are discussed. The most popular neuron models (without training) used in neural network architectures and algorithms (NNA) are considered, focusing on hardware implementation of neuron models used in NAA, and in emulation of biological systems. Mathematical descriptions and block diagram representations are utilized in an independent approach. Nonoscillatory and oscillatory models are discusse

Electronically--implemented coupled logistic maps

The logistic map is a paradigmatic dynamical system originally conceived to model the discrete-time demographic growth of a population, which shockingly, shows that discrete chaos can emerge from trivial low-dimensional non-linear dynamics. In this work, we design and characterize a simple, low-cost, easy-to-handle, electronic implementation of the logistic map. In particular, our implementation allows for straightforward circuit-modifications to behave as different one-dimensional discrete-time systems. Also, we design a coupling block in order to address the behavior of two coupled maps, although, our design is unrestricted to the discrete-time system implementation and it can be generalized to handle coupling between many dynamical systems, as in a complex system. Our findings show that the isolated and coupled maps' behavior has a remarkable agreement between the experiments and the simulations, even when fine-tuning the parameters with a resolution of $\sim 10^{-3}$. We support these conclusions by comparing the Lyapunov exponents, periodicity of the orbits, and phase portraits of the numerical and experimental data for a wide range of coupling strengths and map's parameters.Comment: 8 pages, 10 figure

Automatic generation of hardware Tree Classifiers

Machine Learning is growing in popularity and spreading across different fields for various applications. Due to this trend, machine learning algorithms use different hardware platforms and are being experimented to obtain high test accuracy and throughput. FPGAs are well-suited hardware platform for machine learning because of its re-programmability and lower power consumption. Programming using FPGAs for machine learning algorithms requires substantial engineering time and effort compared to software implementation. We propose a software assisted design flow to program FPGA for machine learning algorithms using our hardware library. The hardware library is highly parameterized and it accommodates Tree Classifiers. As of now, our library consists of the components required to implement decision trees and random forests. The whole automation is wrapped around using a python script which takes you from the first step of having a dataset and design choices to the last step of having a hardware descriptive code for the trained machine learning model

Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed

Modeling of system knowledge for efficient agile manufacturing : tool evaluation, selection and implementation scenario in SMEs

In the manufacturing world, knowledge is fundamental in order to achieve effective and efficient real time decision making. In order to make manufacturing system knowledge available to the decision maker it has to be first captured and then modelled. Therefore tools that provide a suitable means for capturing and representation of manufacturing system knowledge are required in several types of industrial sectors and types of company’s (large, SME). A literature review about best practice for capturing requirements for simulation development and system knowledge modeling has been conducted. The aim of this study was to select the best tool for manufacturing system knowledge modelling in an open-source environment. In order to select this tool, different criteria were selected, based on which several tools were analyzed and rated. An exemplary use case was then developed using the selected tool, Systems Modeling Language (SysML). Therefore, the best practice has been studied, evaluated, selected and then applied to two industrial use cases by the use of a selected opens source tool.peer-reviewe

Causality in real-time dynamic substructure testing

Causality, in the bond graph sense, is shown to provide a conceptual framework for the design of real-time dynamic substructure testing experiments. In particular, known stability problems with split-inertia substructured systems are reinterpreted as causality issues within the new conceptual framework. As an example, causality analysis is used to provide a practical solution to a split-inertia substructuring problem and the solution is experimentally verified

Development of a MATLAB/Simulink - Arduino environment for experimental practices in control engineering teaching

This project presents the steps followed when implementing a platform based on MATLAB/Simulink and Arduino for the restoration of digital control practices. During this project, an Arduino shield has being designed. Along with this, a web page has also been created where all the material done during all this project is available and can be freely used. So anyone interested on doing a project can have a starting point instead of starting a project from scratch, which most of times this results hard to implement. Taking all this into account, the document is structured in the following manner. The first chapter talks about the hardware used and designed. The second one explains the software used and the configurations done on the laboratory’s PCs. After that, the web page Duino-Based Learning is explained, where you can find the five projects carried out in the "Control Automàtic" subject with their corresponding results. In this section too, as an additional research, the implemented indirect adaptive control will be explained, where the parameter estimation has been done by the Recursive Least Square algorithm. The last four sections before presenting the conclusions of the work, correspond to a satisfaction questionnaire done to the teachers that have used the setup, the costs and saves of the project, the environmental impact and the planning of the project respectively

To develop an efficient variable speed compressor motor system

This research presents a proposed new method of improving the energy efficiency of a Variable Speed Drive (VSD) for induction motors. The principles of VSD are reviewed with emphasis on the efficiency and power losses associated with the operation of the variable speed compressor motor drive, particularly at low speed operation.The efficiency of induction motor when operated at rated speed and load torque is high. However at low load operation, application of the induction motor at rated flux will cause the iron losses to increase excessively, hence its efficiency will reduce dramatically. To improve this efficiency, it is essential to obtain the flux level that minimizes the total motor losses. This technique is known as an efficiency or energy optimization control method. In practice, typical of the compressor load does not require high dynamic response, therefore improvement of the efficiency optimization control that is proposed in this research is based on scalar control model.In this research, development of a new neural network controller for efficiency optimization control is proposed. The controller is designed to generate both voltage and frequency reference signals imultaneously. To achieve a robust controller from variation of motor parameters, a real-time or on-line learning algorithm based on a second order optimization Levenberg-Marquardt is employed. The simulation of the proposed controller for variable speed compressor is presented. The results obtained clearly show that the efficiency at low speed is significant increased. Besides that the speed of the motor can be maintained. Furthermore, the controller is also robust to the motor parameters variation. The simulation results are also verified by experiment