Analog‐to‐Digital Conversion for Cognitive Radio: Subsampling, Interleaving, and Compressive Sensing

This chapter explores different analog-to-digital conversion techniques that are suitable to be implemented in cognitive radio receivers. This chapter details the fundamentals, advantages, and drawbacks of three promising techniques: subsampling, interleaving, and compressive sensing. Due to their major maturity, subsampling- and interleaving-based systems are described in further detail, whereas compressive sensing-based systems are described as a complement of the previous techniques for underutilized spectrum applications. The feasibility of these techniques as part of software-defined radio, multistandard, and spectrum sensing receivers is demonstrated by proposing different architectures with reduced complexity at circuit level, depending on the application requirements. Additionally, the chapter proposes different solutions to integrate the advantages of these techniques in a unique analog-to-digital conversion process

Time interleaved counter analog to digital converters

The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration

High-Speed Low-Power Analog to Digital Converter for Digital Beam Forming Systems

abstract: Time-interleaved analog to digital converters (ADCs) have become critical components in high-speed communication systems. Consumers demands for smaller size, more bandwidth and more features from their communication systems have driven the market to use modern complementary metal-oxide-semiconductor (CMOS) technologies with shorter channel-length transistors and hence a more compact design. Downscaling the supply voltage which is required in submicron technologies benefits digital circuits in terms of power and area. Designing accurate analog circuits, however becomes more challenging due to the less headroom. One way to overcome this problem is to use calibration to compensate for the loss of accuracy in analog circuits. Time-interleaving increases the effective data conversion rate in ADCs while keeping the circuit requirements the same. However, this technique needs special considerations as other design issues associated with using parallel identical channels emerge. The first and the most important is the practical issue of timing mismatch between channels, also called sample-time error, which can directly affect the performance of the ADC. Many techniques have been developed to tackle this issue both in analog and digital domains. Most of these techniques have high complexities especially when the number of channels exceeds 2 and some of them are only valid when input signal is a single tone sinusoidal which limits the application. This dissertation proposes a sample-time error calibration technique which bests the previous techniques in terms of simplicity, and also could be used with arbitrary input signals. A 12-bit 650 MSPS pipeline ADC with 1.5 GHz analog bandwidth for digital beam forming systems is designed in IBM 8HP BiCMOS 130 nm technology. A front-end sample-and-hold amplifier (SHA) was also designed to compare with an SHA-less design in terms of performance, power and area. Simulation results show that the proposed technique is able to improve the SNDR by 20 dB for a mismatch of 50% of the sampling period and up to 29 dB at 37% of the Nyquist frequency. The designed ADC consumes 122 mW in each channel and the clock generation circuit consumes 142 mW. The ADC achieves 68.4 dB SNDR for an input of 61 MHz.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Wideband CMOS Data Converters for Linear and Efficient mmWave Transmitters

With continuously increasing demands for wireless connectivity, higher\ua0carrier frequencies and wider bandwidths are explored. To overcome a limited transmit power at these higher carrier frequencies, multiple\ua0input multiple output (MIMO) systems, with a large number of transmitters\ua0and antennas, are used to direct the transmitted power towards\ua0the user. With a large transmitter count, each individual transmitter\ua0needs to be small and allow for tight integration with digital circuits. In\ua0addition, modern communication standards require linear transmitters,\ua0making linearity an important factor in the transmitter design.In this thesis, radio frequency digital-to-analog converter (RF-DAC)-based transmitters are explored. They shift the transition from digital\ua0to analog closer to the antennas, performing both digital-to-analog\ua0conversion and up-conversion in a single block. To reduce the need for\ua0computationally costly digital predistortion (DPD), a linear and wellbehaved\ua0RF-DAC transfer characteristic is desirable. The combination\ua0of non-overlapping local oscillator (LO) signals and an expanding segmented\ua0non-linear RF-DAC scaling is evaluated as a way to linearize\ua0the transmitter. This linearization concept has been studied both for\ua0the linearization of the RF-DAC itself and for the joint linearization of\ua0the cascaded RF-DAC-based modulator and power amplifier (PA) combination.\ua0To adapt the linearization, observation receivers are needed.\ua0In these, high-speed analog-to-digital converters (ADCs) have a central\ua0role. A high-speed ADC has been designed and evaluated to understand\ua0how concepts used to increase the sample rate affect the dynamic performance

Compensation numérique pour convertisseur large bande hautement parallélisé.

Time-interleaved analog-to-digital converters (TIADC) seem to be the holy grail of analog-to-digital conversion. Theoretically, their sampling speed can be increased, very simply, by duplicating the sub-converters. The real world is different because mismatches between the converters strongly reduce the TIADC performance, especially when trying to push forward the sampling speed, or the resolution of the converter. Using background digital mismatch calibration can alleviate this limitation. The first part of the thesis is dedicated to studying the sources and effects of mismatches in a TIADC. Performance metrics such as the SNDR and the SFDR are derived as a function of the mismatch levels. In the second part, new background digital mismatch calibration techniques are presented. They are able to reduce the offset, gain, skew and bandwidth mismatch errors. The mismatches are estimated by using the statistical properties of the input signal and digital filters are used to reconstruct the correct output samples. In the third part, a 1.6 GS/s TIADC circuit, implementing offset, gain and skew mismatch calibration, demonstrates a reduction of the mismatch spurs down to a level of -70 dBFS, up to an input frequency of 750 MHz. The circuit achieves the lowest level of mismatches among TIADCs in the same frequency range, with a reasonable power and area, in spite of the overhead caused by the calibration.Les convertisseurs analogique-numérique à entrelacement temporel (TIADC) semblent être une solution prometteuse dans le monde de la conversion analogique-numérique. Leur fréquence d’échantillonnage peut théoriquement être augmentée en augmentant le nombre de convertisseurs en parallèle. En réalité, des désappariements entre les convertisseurs peuvent fortement dégrader les performances, particulièrement à haute fréquence d’échantillonnage ou à haute résolution. Ces défauts d’appariement peuvent être réduits en utilisant des techniques de calibration en arrière-plan. La première partie de cette thèse est consacrée à l’étude des sources et effets des différents types de désappariements dans un TIADC. Des indicateurs de performance tels que le SNDR ou la SFDR sont exprimés en fonction du niveau des désappariements. Dans la deuxième partie, des nouvelles techniques de calibration sont proposées. Ces techniques permettent de réduire les effets des désappariements d’offset, de gain, d’instant d’échantillonnage et de bande passante. Les désappariements sont estimés en se basant sur des propriétés statistiques du signal et la reconstruction des échantillons de sortie se fait en utilisant des filtres numériques. La troisième partie démontre les performance d’un TIADC fonctionnant a une fréquence d’échantillonnage de 1.6 GE/s et comprenant les calibration d’offset, de gain et d’instant d’échantillonnage proposées. Les raies fréquentielles dues aux désappariements sont réduites à un niveau de -70dBc jusqu’à une fréquence d’entrée de 750 MHz. Ce circuit démontre une meilleure correction de désappariements que des circuits similaires récemment publiés, et ce avec une augmentation de puissance consommée et de surface relativement faible

Offset mismatch calibration for TI-ADCs in high-speed OFDM systems

Time-interleaved analog-to-digital converters (TIADCs) are widely used for multi-Gigabit orthogonal frequency division multiplexing (OFDM) based systems because of their attractive high sampling rate and high resolution. However, when not perfectly calibrated, mismatches such as offset mismatch, gain mismatch and timing mismatch between parallel sub-ADCs can significantly degrade the system performance. In this paper, we focus on offset mismatch. We analyze two calibration techniques for the offset mismatch, based on the least-squares (LS) and linear minimum mean-squared error (LMMSE) algorithms assuming an AWGN channel. The simulation results show that our method is capable of improving the BER performance. As expected, the LMMSE estimator outperforms the LS estimator. However, at large offset mismatch levels or low noise level, both estimators converge. In this paper, we derive the condition on the mismatch level for convergence between the two estimators

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique