A Continuous-Time Delta-Sigma ADC for Portable Ultrasound Scanners

A fully differential fourth-order 1-bit continuous-time delta-sigma ADC designed in a 65nm process for portable ultrasound scanners is presented in this paper. The circuit design, implementation and measurements on the fabricated die are shown. The loop filter consists of RC-integrators, programmable capacitor arrays, resistors and voltage feedback DACs. The quantizer contains a pulse generator, a high-speed clocked comparator and a pull-down clocked latch to ensure constant delay in the feedback loop. Using this implementation, a small and low-power solution required for portable ultrasound scanner applications is achieved. The converter has a supply voltage of 1.2V, a bandwidth of 10MHz and an oversampling ratio of 16 leading to an operating frequency of 320MHz. The design occupies a die area of 0.0175mm2. Simulations with extracted parasitics show a SNR of 45.2dB and a current consumption of 489 µA. However, by adding a model of the measurement setup used, the performance degrades to 42.1dB. The measured SNR and current consumption are 41.6dB and 495 µA, which closely fit with the expected simulations. Several dies have been measured, and an estimation of the die spread distribution is given

Optimization of the Noise Transfer Function of Extended-Frequency-Band-Decomposition sigma-delta A/D converters

International audienceFrequency-Band-Decomposition (FBD) is a good candidate to increase the bandwidths of ADC converters based on sigma-delta modulators. Each modulator processes a part of the input signal band and is followed by a digital filter. In the case of large mismatches in the analog modulators, a new solution, called Extended Frequency-Band-Decomposition (EFBD) can be used. This solution allows for, for example, a four percent error in the central frequencies without significant degradation in the performance when the digital processing part is appeared to the analog modulators. A calibration of the digital part is thus required to reach these theoretical performance. This paper will focus on a self-calibration algorithm for an EFBD. The algorithm helps minimize the quantization noise of the EFBD

Low-Power SAR ADCs:Basic Techniques and Trends

With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For analog-to-digital converters (ADCs), the successive approximation register (SAR) architecture plays a prominent role thanks to its ability to combine power efficiency with a simple architecture, a broad application scope, and technology portability. In this review article, the basic design challenges for low-power SAR ADCs are summarized and several design techniques are illustrated. Furthermore, the limitations of SAR ADCs are outlined and hybrid architecture trends, such as noise-shaping SAR ADCs and pipelined SAR ADCs, are briefly introduced and clarified with examples

Resolution Enhancement of VCO-based ADCs by Passive Interpolation and Phase Injection

Proceeding of: 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS), 20-22 November 2019, Bilbao, SpainThis work describes a simple way to improve the resolution of low-pass voltage-controlled-oscillators based analog-to-digital converters (VCO-based ADCs) implemented with ring-oscillators. We propose to insert a passive resistive network into the differential delay cells of the oscillator to get additional interpolated phases. These interpolated phases are then injected to other similar oscillators. By increasing the number of phases coming from all the oscillators, the effective gain of the system is higher and enhances the resolution of the converter. To validate the idea, a prototype of an open-loop VCO-based ADC was built in VerilogA language with ring-oscillators designed with a 65-nm CMOS process. The results of transient simulations were compared to the results of a behavioral ideal model of the system built in MATLAB. As expected, the signal-to-noise ratio (SNR) was improved in concordance with the increase in the number of phases. Finally, it was checked that the proposed circuit used to extract and inject the interpolated phases did not penalize the total power consumption. The proposed circuit structure is particularly suitable for high-bandwidth applications, where the oversampling ratio (OSR) is strongly restricted and the gain is limited because of the oscillator non-linearity. Due to the highly digital nature of the VCO-based ADC structures, this solution may be of special interest to be implemented in new deep-submicron CMOS processes.This work was supported by the CICYT project TEC2017-82653-R, Spain.Publicad

A Low-Power Sigma-Delta Modulator for Healthcare and Medical Diagnostic Applications

This paper presents a switched-capacitor Sigma-Delta modulator designed in 90-nm CMOS technology, operating at 1.2-V supply voltage. The modulator targets healthcare and medical diagnostic applications where the readout of small-bandwidth signals is required. The design of the proposed A/D converter was optimized to achieve the minimum power consumption and area. A remarkable performance improvement is obtained through the integration of a low-noise amplifier with modified Miller compensation and rail-to-rail output stage. The manuscript also presents a set of design equations, from the small-signal analysis of the amplifier, for an easy design of the modulator in different technology nodes. The Sigma-Delta converter achieves a measured 96-dB dynamic range, over a 250-Hz signal bandwidth, with an oversampling ratio of 500. The power consumption is 30 μW, with a silicon area of 0.39 mm²

A Three-Step Resolution-Reconfigurable Hazardous Multi-Gas Sensor Interface for Wireless Air-Quality Monitoring Applications

This paper presents a resolution-reconfigurable wide-range resistive sensor readout interface for wireless multi-gas monitoring applications that displays results on a smartphone. Three types of sensing resolutions were selected to minimize processing power consumption, and a dual-mode front-end structure was proposed to support the detection of a variety of hazardous gases with wide range of characteristic resistance. The readout integrated circuit (ROIC) was fabricated in a 0.18 ??m CMOS process to provide three reconfigurable data conversions that correspond to a low-power resistance-to-digital converter (RDC), a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC), and a 16-bit delta-sigma modulator. For functional feasibility, a wireless sensor system prototype that included in-house microelectromechanical (MEMS) sensing devices and commercial device products was manufactured and experimentally verified to detect a variety of hazardous gases

Successive-approximation-register based quantizer design for high-speed delta-sigma modulators

High-speed delta-sigma modulators are in high demand for applications such as wire-line and wireless communications, medical imaging, RF receivers and high-definition video processing. A high-speed delta-sigma modulator requires that all components of the delta-sigma loop operate at the desired high frequency. For this reason, it is essential that the quantizer used in the delta-sigma loop operate at a high sampling frequency. This thesis focuses on the design of high-speed time-interleaved multi-bit successive-approximation-register (SAR) quantizers. Design techniques for high-speed medium-resolution SAR analog-to-digital converters (ADCs) using synchronous SAR logic are proposed. Four-bit and 8-bit 5 GS/s SAR ADCs have been implemented in 65 nm CMOS using 8-channel and 16-channel time-interleaving respectively. The 4-bit SAR ADC achieves SNR of 24.3 dB, figure-of-merit (FoM) of 638 fJ/conversion-step and 42.6 mW power consumption, while the 8-bit SAR ADC achieves SNR of 41.5 dB, FoM of 191 fJ/conversion-step and 92.8 mW power consumption. High-speed operation is achieved by optimizing the critical path in the SAR ADC loop. A sampling network with a split-array with unit bridge capacitor topology is used to reduce the area of the sampling network and switch drivers

Ultra-low power incremental delta-sigma analog-to-digital converter for self-powered sensor applications

Tässä työssä esitetään ultramatalatehoinen inkrementaalinen delta-sigma-analogia-digitaalimuunnin. Muunnin on suunniteltu 0,18 μm:n CMOS-teknologialla, ja se toimii 1,2 V :n käyttöjännitteellä ja 5 kHz:n kellotaajuudella. Differentiaalinen tulosignaali on käytännössä dc:llä, ja se vaihtelee 600 mV :n yhteismuotoisen jännitteen ympärillä -850 mV :sta 850 mV :iin. Delta-sigmamodulaattorissa käytetään kaksiasteista takaisinkytkettyä integraattorikaskadirakennetta, joka on toteutettu kytketty-kondensaattori-integraattoreilla ja yksibittisellä kvantisoijalla. Muuntimen kvantisointikohinavaatimuksien täyttyminen varmistettiin valitsemalla sopivat kertoimet ja ylinäytteistyssuhde käyttäen MATLAB-simulaatioita yhdessä modulaattorin ideaalisen mallin kanssa. Vahvistinten vähimmäisvaatimukset määritettiin makromallitason simuloinneilla ja kytkinten epäideaalisuudet analysoitiin transistoritason simuloinneilla. Varausinjektion huomattiin aiheuttavan piirissä merkittävää harmonista säröä, joten alalevyn näytteistystä (bottom plate sampling) käytettiin signaaliriippuvan varausinjektion välttämiseksi. Lisäksi ensimmäisen integraattorin vahvistimen tulonsiirrosjännitteen ja matalataajuisen kohinan vähentämiseksi käytettiin hakkuristabilointia (chopper stabilization). Muuntimen suorituskykyä analysoitiin eri prosessikulmissa lämpötiloissa −40 ◦ C, 27 ◦ C ja 85 ◦ C, ja epäsovitusherkkyys määritettiin Monte Carlo -analyysin avulla. Simulaatiotulokset sekä piirikuvion perusteella lasketut parasiittiset resistanssit ja kapasitanssit huomioonottaen, että ilman, osoittavat piirin olevan stabiili ja täyttävän tarkkuusvaatimukset kaikissa simuloiduissa kulmissa. Monta Carlo -analyysin perusteella signaali-kohinasuhde on vähintään 80,05 dB:ä ja harmonisen särön kokonaismäärä on enintään -80.89 dB:ä. Tehonkulutus ei ylitä 1,2 μA:a missään simulaatiossa.In this thesis an ultra-low power incremental delta-sigma analog-to-digital converter is presented. The converter is designed in 0.18 μm CMOS technology with a single 1.2 V supply voltage, and it operates with a 5 kHz clock signal. The differential input signal to the converter is virtually dc, and it varies from −850 mV to 850 mV around a common-mode voltage of 600 mV . The delta-sigma modulator has a second order cascade-of-integrators feedback structure, which is realized with switched-capacitor integrators and a one-bit quantizer. The converter’s quantization noise requirement is met by appropriate choice of coefficients and oversampling ratio, based on MATLAB simulations on an ideal model of the modulator. The minimum requirements of the amplifiers were determined from simulations with macromodels, and the switch non-idealities were analyzed in transistor-level simulations. It was noticed that switch charge injection causes significant harmonic distortion in the circuit, hence bottom plate sampling was implemented to eliminate the signal-dependent charge injection. Furthermore, the offset and low-frequency noise in the first integrator were attenuated by means of chopper stabilization. The converter’s performance is analyzed in different process corners, at −40◦ C, 27◦ C, and 85◦ C, and its process mismatch sensitivity is determined via Monte Carlo analysis. The results obtained from both pre- and post-layout simulations indicate complete stability, and acceptable accuracy in all design corners. The minimum signal-to-noise and distortion ratio obtained from corner analysis, is 80.05 dB, which is enhanced up to 7 dB in the best corner, and maximum harmonic distortion is below −80.89 dB. Moreover, the power consumption of the converter did not exceed 1.2 μW in any of the simulations

VCO-based ADCs Design Techniques for Communication Systems

This work presents a novel technique to implement voltage-controlled oscillator based continuous-time Delta-Sigma analog-to-digital converters (VCO-based CT-ΔΣ ADCs) in closed-loop configuration. Over the past years there has been an upward trend in the use of these type of converters for instrumentation, audio and communication applications. The reason is that they are mostly digital and thus benefit from advances in deep-submicron CMOS processes. VCO-based ADCs have been widely studied in a great deal of papers and it is known that one of its main drawbacks is the non-linearity it presents. To overcome this issue, to place the VCO within a closed-loop is usually done to attenuate its input magnitude level. However, to do so it is needed a digital-to-analog converter (DAC) as in a conventional CT-ΔΣ, therefore it is required for the DAC to be simple and it cannot present a high number of elements, being the latter a bottleneck for implementing VCOs with a high number of inverters. This works presents a technique that enables to use VCOs with severals inverters while keeping the same number of DAC elements as before. Based upon previous theoretical studies of the VCO-based ADCs which model it as a pulse frequency modulation encoder, this new technique is analyzed and linear models are developed in order to study its viability at system level. Moreover, how impairments related to a real implementation affect the use of this technique are also analyzed. The contributions proposed in this document are focused but not limited to communication applications.Máster Universitario en Ingeniería de Sistemas Electrónicos y Aplicaciones. Curso 2018/201

Design of a Reference Buffer for a Delta-Sigma ADC with Current DAC

In analog to digital conversion, it’s necessary to provide a reference voltage to the Analog to Digital Converter (ADC), in order to quantify the input signal. However, as the ADC has a switch constantly commuting on its input it will cause perturbations on the reference voltage provided by the Bandgap circuit. Thus, it will interfere with the normal behaviour of the Bandgap circuit, which will longer be capable of provide the desired reference voltage. Besides, if the reference voltage is not constant in the desired value the output code generated by the ADC will have errors. In order to avoid conversion errors it will be needed to introduce a buffer between the Bandgap and the ADC. Thus, taking advantage from the characteristics of the buffer (low output impedance, high input impedance and unitary gain) the system will be capable of recover from the perturbations introduced by the ADC in the reference voltage. Therefore, in this thesis are studied some of the already existing architectures of buffers, in order to see the advantages and disadvantages of each one. This way were chosen the best three architectures from a theoretical point of view, to implement and simulate, to obtain all the needed information in order to better compare them