Designing PID controller using SSA for interconnected thermal power systems

This article presents a method of designing an optimal Proportional-Integral-Derivative (PID) controller for Automatic Generation Control (AGC) of a two-area interconnected thermal system. In addition, an application of Salp Swarm Algirithm (SSA) in order to design PID controllers is proposed. A method inspired by salp foraging behavior. The journey of the Salp group in the sea, by random the population of the salp and separated into leader salp and follower salp. The leader moves towards the food source and the rest of the followers follow the salp positioned in front of themselves. The parameters of PID were achieved by trial and error methods by designers. As an interconneted thermal power system with a Governor Deadband (GDB) is nonlinear and dynamic system, the Integral Squared Error (ISE) criterion has been used as objective function to find optimum controller gain. In order to solve this problem, SSA is proposed to concurrently tune PID gains of the PID controllers to minimize frequency deviations and tie-line power deviations by simulation the interconnected thermal power system .Compare of tuning PID controller from each optimization technique SSA and PSO .Simulation results clearly show that the performance of the system after taking SLP into the interconnected thermal power system that tuning by SSA and PSO and the robustness of the optimal PID controllers are superior to the conventional PID controllers in terms of settling time (–10.46 % in area 1, +0.87 % in area 2 and +0.57 % in power tie-line), overshoot (–10.61 % in area 1 and –10.87 % in area 2) that obtain by (SSA) method less value than the value that obtain by (PSO) method and the power tie-line. Integral Absolute Error (IAE) (–0.38 %) that obtain by (SSA) few errors. Comparisons to the tuned with Particle Swarm Optimization (PSO) approaches is also include

A fully balanced first order high-pass filter

The topic of this article is the design of a fully balanced first-order high-pass filter and its two circuits. The first circuit is a fully balanced current-tunability first-order high-pass filter consisting of four NPN transistors and a single capacitor, which is a simple design and quite compact. The pole frequency can be adjusted with a bias current. The results of the first circuit shows the phase and gain responses, the phase and gain responses when adjusted with a bias current, the time-domain response, and the harmonic spectrum. However, this circuit found a flaw in the temperature that affects the pole frequency, and total harmonic distortion is relatively high. Therefore, the second circuit improves defects by the CAPRIO technique to reduce the total harmonic distortion, and the resistors in the circuit are added to the design to replace the resistance and the effect of temperature on the properties of the transistor. This circuit consists of four NPN transistors, four resistors, and a single capacitor. The resistors in this circuit can be adjusted to change the pole frequency and voltage gain. The results of the second circuit show the gain and phase responses of the proposed circuits, the phase and gain responses when adjusted to the value of the resistor, the phase and gain responses at various temperatures, as well as their time-domain responses and total harmonic signal distortion. The all-pass filter is also made using the filter introduced in the second circuit because of its voltage gain-adjustable property. So, if the suggested circuit is constructed in combination with a buffer circuit to make it feasible to function as an all-pass filter, the result will be an all-pass filter. In accordance with the results of this study, we have introduced a design for a high-pass filter to reduce total harmonic distortion and the effect of temperatur