A Compact Electromagnetic Vibration Harvesting System with High Performance Interface Electronics

A compact vibration-based electromagnetic (EM) energy harvesting system utilizing high performance interface electronics, has been presented. The energy harvester module consists of an AA-battery sized cylinder tube with an external coil winding, a fixed magnet at the bottom of the tube, and a free magnet inside. The transducer is able to operate at low external vibration frequencies between 9.5 and 12 Hz. The generated AC voltage is converted to DC using a custom rectifier circuit that utilizes a gate cross coupled (GCC) input stage. This decreases the effective threshold voltage of the utilized diodes, while increasing the DC output power delivered to the load. The autonomous system, composed of an EM energy harvester module and a 0.35 mu m CMOS IC, delivers 11.6 mu W power to a 41 mu A load at an external vibration frequency of 12 Hz. The volume of the total system is 4.5 cm(3), and the overall system power density is 2.6 mu W/cm(3)

Acute diverticulitis in immunocompromised patients: evidence from an international multicenter observational registry (Web-based International Register of Emergency Surgery and Trauma, Wires-T)

Background: Immunocompromised patients with acute diverticulitis are at increased risk of morbidity and mortality. The aim of this study was to compare clinical presentations, types of treatment, and outcomes between immunocompromised and immunocompetent patients with acute diverticulitis. Methods: We compared the data of patients with acute diverticulitis extracted from the Web-based International Registry of Emergency Surgery and Trauma (WIRES-T) from January 2018 to December 2021. First, two groups were identified: medical therapy (A) and surgical therapy (B). Each group was divided into three subgroups: nonimmunocompromised (grade 0), mildly to moderately (grade 1), and severely immunocompromised (grade 2). Results: Data from 482 patients were analyzed—229 patients (47.5%) [M:F = 1:1; median age: 60 (24–95) years] in group A and 253 patients (52.5%) [M:F = 1:1; median age: 71 (26–94) years] in group B. There was a significant difference between the two groups in grade distribution: 69.9% versus 38.3% for grade 0, 26.6% versus 51% for grade 1, and 3.5% versus 10.7% for grade 2 (p < 0.00001). In group A, severe sepsis (p = 0.027) was more common in higher grades of immunodeficiency. Patients with grade 2 needed longer hospitalization (p = 0.005). In group B, a similar condition was found in terms of severe sepsis (p = 0.002), quick Sequential Organ Failure Assessment score > 2 (p = 0.0002), and Mannheim Peritonitis Index (p = 0.010). A Hartmann’s procedure is mainly performed in grades 1–2 (p < 0.0001). Major complications increased significantly after a Hartmann’s procedure (p = 0.047). Mortality was higher in the immunocompromised patients (p = 0.002). Conclusions: Immunocompromised patients with acute diverticulitis present with a more severe clinical picture. When surgery is required, immunocompromised patients mainly undergo a Hartmann’s procedure. Postoperative morbidity and mortality are, however, higher in immunocompromised patients, who also require a longer hospital stay

Nurses' perceptions of aids and obstacles to the provision of optimal end of life care in ICU

Contains fulltext : 172380.pdf (publisher's version ) (Open Access

Physiological parameters for Prognosis in Abdominal Sepsis (PIPAS) Study : a WSES observational study

BackgroundTiming and adequacy of peritoneal source control are the most important pillars in the management of patients with acute peritonitis. Therefore, early prognostic evaluation of acute peritonitis is paramount to assess the severity and establish a prompt and appropriate treatment. The objectives of this study were to identify clinical and laboratory predictors for in-hospital mortality in patients with acute peritonitis and to develop a warning score system, based on easily recognizable and assessable variables, globally accepted.MethodsThis worldwide multicentre observational study included 153 surgical departments across 56 countries over a 4-month study period between February 1, 2018, and May 31, 2018.ResultsA total of 3137 patients were included, with 1815 (57.9%) men and 1322 (42.1%) women, with a median age of 47years (interquartile range [IQR] 28-66). The overall in-hospital mortality rate was 8.9%, with a median length of stay of 6days (IQR 4-10). Using multivariable logistic regression, independent variables associated with in-hospital mortality were identified: age > 80years, malignancy, severe cardiovascular disease, severe chronic kidney disease, respiratory rate >= 22 breaths/min, systolic blood pressure 4mmol/l. These variables were used to create the PIPAS Severity Score, a bedside early warning score for patients with acute peritonitis. The overall mortality was 2.9% for patients who had scores of 0-1, 22.7% for those who had scores of 2-3, 46.8% for those who had scores of 4-5, and 86.7% for those who have scores of 7-8.ConclusionsThe simple PIPAS Severity Score can be used on a global level and can help clinicians to identify patients at high risk for treatment failure and mortality.Peer reviewe

Power Delay Product Optimized Hybrid Full Adder Circuits

Data processing performed by adder circuits need to achieve low delay and low power at the same time while maintaining low cost, due to the steep growth in mobile computation devices. Recently proposed 1-bit full adder design that hybridizes transmission gates (TG) and standard CMOS offers significant PDP improvement. Two full adder implementations are presented in this paper which further optimizes the previously presented circuits: First (CKT1) deploys GDI-cell based XNOR module to decrease PDP, while the second circuit (CKT2) reduces the worst case delay with equivalent PDP. Simulation results indicate the proposed CKT1 has 4.8% and 2.5% reduced PDP for realistic cascade and FO4 loads respectively, with 16% improved cost compared to literature. CKT2 maintains comparable PDP with 11.3% and 2% improved delay for realistic cascade and FO4 loads respectively

PETAM: Power estimation tool for array multipliers

Increasing demand for the mobile, low energy systems has laid emphasis on the development of low power processors. Low power design has to be incorporated into fundamental computation units, such as multipliers. The optimization of the energy-delay product in such low power multipliers will enable energy efficient computation. This study proposes a power estimation tool to analyze different array multiplier architectures, which are most commonly used in such applications. Gate level library design parameters are utilized to derive energy-delay performance for any given set of input vector patterns, and multiplier size. Vector and size dependent factors are therefore clearly identified. Examples are provided from carry save array multiplier (CSAM) and ripple carry array multiplier (RCAM) to demonstrate the capabilities for the tool. © 2012 IEEE

Feasibility analysis and proof of concept for thermoelectric energy harvesting in mobile computers

Thermoelectric (TE) energy harvesting in compact microelectronic systems necessitates detailed upfront analysis to ensure unacceptable performance degradation is avoided. TE integration into a notebook computer is empirically investigated in this work for energy harvesting. A detailed finite element model was constructed first for thermal simulations. The model outputs were then correlated with the thermal validation results of the selected system. In parallel, a commercial TE micro-module was empirically characterized to quantify maximum power generation opportunity from the combined system and component data set. Next, suitable "warm spots" were identified within the mobile computer model to extract TE power with minimum or no notable impact to system performance, as measured by simulated thermal changes in the system. The prediction was validated by integrating a TE micro-module to the mobile system under test. Measured TE power generation density in the vicinity of the heat pipe was 1.26 mW/cm(3) using high CPU load. The generated power scales down with lower CPU activity, and will scale up in proportion to the utilized opportunistic space within the system. The technical feasibility of TE energy harvesting in mobile computers has hence been experimentally proven for the first time. (C) 2013 American Institute of Physics. [http://dx.doi.org/10.1063/1.4794751

Empirical feasibility analysis of thermoelectric energy harvesting in thermally limited compact mobile computers

Thermoelectric (TE) generation technology was experimentally established in previous research by our group as a viable technique for energy scavenging in a large notebook computer with no significant impact to system performance. The computer under investigation was designed to have additional thermal headroom, with Central Processing Unit (CPU) temperature significantly below its maximum limit under maximum workload conditions. Yet the question remained on if and how such scavenging could be done in small, thermally limited systems, which increasingly represent a larger portion of the contemporary microelectronic products. This paper thus empirically demonstrates the feasibility of thermoelectric energy scavenging in a compact mobile system, where CPU temperature readily reaches the maximum limit as the workload activity is increased. A detailed Finite Element model is presented first for what-if studies. The simulation results from the model are then correlated with the experimental thermal characterization data from a small notebook computer. "Hotspots" as well as the plausible locations for TE integration are identified in the system through the thermal simulations, and are validated by integrating the TE module to the target system. TE power generation density has been measured as 4.27 mW/cm(3) under maximum workload conditions with no impact to system performance, as measured indirectly through cooling fan speed, CPU, and integrated graphics temperatures. For a well-characterized off-the-shelf TE component of size 6.05mm x 6.05mm x 2.09mm, the maximum generated power was 410.5 mu W, 3.5 times more than the corresponding value measured previously in the large notebook system under the same workload. Harvested power is expected to scale with the system workload activity, and the extension of the current solution to the similar opportunistic locations within the system. (C) 2014 AIP Publishing LLC

A self-powered integrated interface circuit for low power piezoelectric energy harvesters

This paper presents a CMOS integrated interface circuit for piezoelectric energy harvesters (PEH). A fully self-powered circuit, based on Synchronous Electric Charge extraction (SECE) technique, is implemented for non-resonant piezoelectric harvesters generating low power, in 10s to 100s mu W range. The circuit is realized in standard 180 nm UMC CMOS technology. A switch control circuit is designed and optimized to extract maximum power independently from excitation changes of the PEH. The total power loss of the switch control circuit is reduced to 3.6 mu W. The simulations with an output voltage range of 1.1 to 4 V show maximum power conversion efficiency of 83% (at 4 V) for a higher power PEH module, and maximum power conversion efficiency of 75% (at 2.6 V) for a lower power PEH module