A Simple Technique for Fast Digital Background Calibration of A/D Converters

A modification of the background digital calibration procedure for A/D converters by Li and Moon is proposed, based on a method to improve the speed of convergence and the accuracy of the calibration. The procedure exploits a colored random sequence in the calibration algorithm, and can be applied both for narrowband input signals and for baseband signals, with a slight penalty on the analog bandwidth of the converter. By improving the signal-to-calibration-noise ratio of the statistical estimation of the error parameters, our proposed technique can be employed either to improve linearity or to make the calibration procedure faster. A practical method to generate the random sequence with minimum overhead with respect to a simple PRBS is also presented. Simulations have been performed on a 14-bit pipeline A/D converter in which the first 4 stages have been calibrated, showing a 15 dB improvement in THD and SFDR for the same calibration time with respect to the original technique

A power efficient frequency divider with 55 GHz self-oscillating frequency in SiGe BiCMOS

A power efficient static frequency divider in commercial 55 nm SiGe BiCMOS technology isreported. A standard Current Mode Logic (CML)-based architecture is adopted, and optimizationof layout, biasing and transistor sizes allows achieving a maximum input frequency of 63 GHz anda self-oscillating frequency of 55 GHz, while consuming 23.7 mW from a 3 V supply. This resultsin high efficiency with respect to other static frequency dividers in BiCMOS technology presentedin the literature. The divider topology does not use inductors, thus optimizing the area footprint:the divider core occupies 60×65μm2on silicon

A 0.3 V rail-to-rail ultra-low-power OTA with improved bandwidth and slew rate

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier

Genome-wide Analyses Identify KIF5A as a Novel ALS Gene

To identify novel genes associated with ALS, we undertook two lines of investigation. We carried out a genome-wide association study comparing 20,806 ALS cases and 59,804 controls. Independently, we performed a rare variant burden analysis comparing 1,138 index familial ALS cases and 19,494 controls. Through both approaches, we identified kinesin family member 5A (KIF5A) as a novel gene associated with ALS. Interestingly, mutations predominantly in the N-terminal motor domain of KIF5A are causative for two neurodegenerative diseases: hereditary spastic paraplegia (SPG10) and Charcot-Marie-Tooth type 2 (CMT2). In contrast, ALS-associated mutations are primarily located at the C-terminal cargo-binding tail domain and patients harboring loss-of-function mutations displayed an extended survival relative to typical ALS cases. Taken together, these results broaden the phenotype spectrum resulting from mutations in KIF5A and strengthen the role of cytoskeletal defects in the pathogenesis of ALS.Peer reviewe

High‐gain, high‐CMRR class AB operational transconductance amplifier based on the flipped voltage follower

A novel class AB operational transconductance amplifier (OTA) topology is proposed, based on a class AB flipped voltage follower. The OTA has class AB behavior, with current boosting both for the load and the compensation capacitors. It has a high gain of (gmr0)4, obtained using a two‐stage structure with cascoded stages, and is a two‐stage Miller‐compensated amplifier employing multipath to remove the positive zero. It has close to rail‐to‐rail output swing (limited by cascoding) and very low common‐mode gain thanks to a replica technique (allowing the use of low‐power common‐mode feedback [CMFB] loops). Ninety‐two decibels of gain and 176 dB of common‐mode rejection ratio (CMRR) without CMFB are achieved using a 40‐nm complementary metal‐oxide semiconductor (CMOS) process. The OTA is used to design a low‐power sample‐and‐hold amplifier (SHA) operating at 5 MSps, a typical application for CMOS OTAs, which has been chosen to verify the proposed circuit's performance and to show that the OTA is robust in Monte Carlo simulations under process variations and mismatches in an actual application

A 10 GHz inductorless active SiGe HBT lowpass filter

High-frequency (around 10 GHz) filters are necessary for many applications, in anti-aliasing filters for high-speed data converters or optical communications. Modern SiGe technology allows implementing radio-frequency circuits up to about 100 GHz. At the lower frequencies around 10 GHz, the size of passive components is a concern, and inductorless designs are used. We present a topology for an inductorless lowpass biquad filter capable of operating at 10 GHz or more in the STMicroelectronics BiCMOS55 process. The filter is simulated considering temperature, process, biasing and mismatch variations, tested with parametric and Monte Carlo simulations. The layout of the biquad filter has been implemented, and the results of post-layout simulations are reported. The biquad stage has good dynamic range (45 dB) and power efficiency (0.65 pW/Hz/pole) with respect to comparable active lowpass filters reported in the literature, and, unlike other filters, only uses NPN devices, which are the only high-speed devices available in many Hybrid Bipolar Transistor (HBT) technologies

Two novel architectures for 4-channel mixing/filtering/processing digitizers

Two architectures of 4-channel mixing-filtering-processing (MFP) digitizers are presented and compared. Both architectures use four analogue-to-digital converters (ADCs), but differ in terms of layout, and are named parallel and hierarchical, respectively. The hierarchical architecture is entirely novel, while the parallel one is at present only envisaged in patent documents. For both architectures, a suitable analytical model, used to determine the effects of several error sources, is provided. Also, digital signal processing techniques, which combine the digitized streams produced by the four ADCs to compensate the errors, are illustrated for both architectures. The computational cost of these techniques, implemented by means of poly-phase filters, is discussed, and their capability of attaining real time performance highlighted. The results of behavioral simulations carried out to assess the performance of the two 4-channel MFP architectures are finally shown