Reducing instruction fetch energy with backwards branch control information and buffering

Many emerging applications, e.g. in the embedded and DSP space, are often characterized by their loopy nature where a substantial part of the execution time is spent within a few program phases. Loop buffering techniques have been proposed for capturing and processing these loops in small buffers to reduce the processor‘s instruction fetch energy. However, these schemes are limited to straight-line or inner-most loops and fail to adequately handle complex loops. In this paper, we propose a dynamic loop buffering mech-anism that uses backwards branch control information to identify, capture and process complex loop structures. The DLB controller has been fully implemented in VHDL, syn-thesized and timed with the IBM Booledozer and Einstimer Synthesis tools, and analyzed for power with the Sequence PowerTheater tool. Our experiments show that the DLB approach, on average, results in a factor of 3 reduction in energy consumption compared to a traditional instruction memory design at an area overhead of about 9%

Flexible Timing Simulation of Multiple-Cache Configurations

Abstract As the gap between processor and memory speeds increases, cache performance becomes more critical to overall system performance. Behavioral cache simulation is typically used early in the design cycle of new processor/cache configurations to determine the performance of proposed cache configurations on target workloads. However, behavioral cache simulation does not account for the latency seen by each memory access. The Latency-Effects (LE) cache model presented in this paper accounts this nominal latency as well as the additional latencies due to trailing-edge effects, bus width considerations, port conflicts, and the number of outstanding accesses that a cache allows before it blocks. We also extend the LE cache model to handle the latency effects of moving data among multiple caches. mlcache, a new, easily configurable and extensible tool, has been built based on the extended LE model. We show the use of mlcache in estimating the performance of traditional and novel cache configurations, including odd/even, 2-level, Assist, Victim, and NTS caches. We also show how the LE cache timing model provides more useful, realistic performance estimates than other possible behavioral-level cache timing models. Keywords: cache timing simulation model evaluation Introduction Cache performance becomes ever more critical to overall system performance as the gap between processor and memory speed increases. The performance of a particular cache configuration depends not only on the miss ratio incurred during the execution of a particular workload but also on where in the program's execution the misses occur and the latency of each miss. However, useful timing simulation of caches is typically unavailable until late in the design stage. Using today's behavioral simulators, simple, traditional caches are evaluated early in the design cycle; however, novel cache designs are often not considered since they are difficult to model. The issue of providing more useful cache timing simulation analysis early in the design cycle has been addressed by the Latency-Effects (LE) cache model [Tam96], which incorporates latency-adding effects into a behavioral-level simulation, particularly trailing-edge effects, bus width considerations, the effects of port conflicts, and the number of outstanding accesses that a cache can handle before blocking. Existing methods of modifying behavioral cache simulators to incorporate timing effects include adjusting the total cycle count reported by a perfect cache simulation by adding an estimated number of cycles due to cache misses (the adjusted model) or assigning a nominal leading-edge penalty to each miss as it occurs (a model we will refer to as LEnominal). To illustrate the advantages of the LE cache model, we will compare the LE cache model's results to the results of using these other models. 1. This research was funded in part by a gift from IBM

Whole-genome sequencing reveals host factors underlying critical COVID-19

Critical COVID-19 is caused by immune-mediated inflammatory lung injury. Host genetic variation influences the development of illness requiring critical care1 or hospitalization2–4 after infection with SARS-CoV-2. The GenOMICC (Genetics of Mortality in Critical Care) study enables the comparison of genomes from individuals who are critically ill with those of population controls to find underlying disease mechanisms. Here we use whole-genome sequencing in 7,491 critically ill individuals compared with 48,400 controls to discover and replicate 23 independent variants that significantly predispose to critical COVID-19. We identify 16 new independent associations, including variants within genes that are involved in interferon signalling (IL10RB and PLSCR1), leucocyte differentiation (BCL11A) and blood-type antigen secretor status (FUT2). Using transcriptome-wide association and colocalization to infer the effect of gene expression on disease severity, we find evidence that implicates multiple genes—including reduced expression of a membrane flippase (ATP11A), and increased expression of a mucin (MUC1)—in critical disease. Mendelian randomization provides evidence in support of causal roles for myeloid cell adhesion molecules (SELE, ICAM5 and CD209) and the coagulation factor F8, all of which are potentially druggable targets. Our results are broadly consistent with a multi-component model of COVID-19 pathophysiology, in which at least two distinct mechanisms can predispose to life-threatening disease: failure to control viral replication; or an enhanced tendency towards pulmonary inflammation and intravascular coagulation. We show that comparison between cases of critical illness and population controls is highly efficient for the detection of therapeutically relevant mechanisms of disease

Genetic mechanisms of critical illness in COVID-19.

Host-mediated lung inflammation is present1, and drives mortality2, in the critical illness caused by coronavirus disease 2019 (COVID-19). Host genetic variants associated with critical illness may identify mechanistic targets for therapeutic development3. Here we report the results of the GenOMICC (Genetics Of Mortality In Critical Care) genome-wide association study in 2,244 critically ill patients with COVID-19 from 208 UK intensive care units. We have identified and replicated the following new genome-wide significant associations: on chromosome 12q24.13 (rs10735079, P = 1.65 × 10-8) in a gene cluster that encodes antiviral restriction enzyme activators (OAS1, OAS2 and OAS3); on chromosome 19p13.2 (rs74956615, P = 2.3 × 10-8) near the gene that encodes tyrosine kinase 2 (TYK2); on chromosome 19p13.3 (rs2109069, P = 3.98 ×  10-12) within the gene that encodes dipeptidyl peptidase 9 (DPP9); and on chromosome 21q22.1 (rs2236757, P = 4.99 × 10-8) in the interferon receptor gene IFNAR2. We identified potential targets for repurposing of licensed medications: using Mendelian randomization, we found evidence that low expression of IFNAR2, or high expression of TYK2, are associated with life-threatening disease; and transcriptome-wide association in lung tissue revealed that high expression of the monocyte-macrophage chemotactic receptor CCR2 is associated with severe COVID-19. Our results identify robust genetic signals relating to key host antiviral defence mechanisms and mediators of inflammatory organ damage in COVID-19. Both mechanisms may be amenable to targeted treatment with existing drugs. However, large-scale randomized clinical trials will be essential before any change to clinical practice

Are identities oral? Understanding ethnobotanical knowledge after Irish independence (1937-1939)

BACKGROUND: The Schools' Folklore Scheme (1937-1939) was implemented at a pivotal time in Irelands' political history. It resulted in a body of ethnological information that is unique in terms of when, why and how it was collected. This material consists of over 700,000 pages of information, including ethnomedicinal and ethnobotanical traditions, reflecting an oral identity that spans generations and that in many cases was not documented in writing until the 1930s. The intention of this study is to highlight the importance of the Schools' Folklore Scheme and to demonstrate an ethnographic approach based on recollections of original participants of the scheme, to further understand the material in the collection and the impact it had on the participants. METHODS: This study involves an analysis of both oral and archival data. Eleven semi-structured interviews with original participants of the scheme were carried out between April and September 2016. Their corresponding schools' archival contributions to the scheme were located, and ethnomedicinal information was analysed and compared with the participants' recollections. RESULTS: The majority of participants' stated the scheme had a positive impact on them. Five participants' recalled collecting ethnomedicinal information, and there was a direct correlation between three of the participants' ethnomedicinal recollections and their entries in the archives. One third of all the ethnomedicinal entries analysed included the use of a plant. There were 191 plant mentions and 64 plant species named. CONCLUSIONS: Contacting the original participants offers a novel approach of analysing this archival material. It provides a unique first-hand account of this historical initiative, an insight into how the scheme was implemented and how it impacted upon the children. The ethnomedicinal and ethnobotanical information provides an understanding of the medicinal practices in Ireland during the 1930s. The plant species that were both orally recalled by participants and documented in the archives are in keeping with key ethnomedicinal systems throughout the world

Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions

This paper concerns the validity of a widely used method for estimating the architecture-level mean time to failure (MTTF) due to soft errors. The method first calculates the failure rate for an architecture-level component as the product of its raw error rate and an architecture vulnerability factor (AVF). Next, the method calculates the system failure rate as the sum of the failure rates (SOFR) of all components, and the system MTTF as the reciprocal of this failure rate. Both steps make significant assumptions. We investigate the validity of the AVF+SOFR method across a large design space, using both mathematical and experimental techniques with real program traces from SPEC 2000 benchmarks and synthesized traces to simulate longer real-world workloads. We show that AVF+SOFR is valid for most of the realistic cases under current raw error rates. However, for some realistic combinations of large systems, long-running workloads with large phases, and/or large raw error rates, the MTTF calculated using AVF+SOFR shows significant discrepancies from that using first principles. We also show that SoftArch, a previously proposed alternative method that does not make the AVF+SOFR assumptions, does not exhibit the above discrepancies

Metrics for Lifetime Reliability

This work concerns appropriate metrics for evaluating microarchitectural enhancements to improve processor lifetime reliability. The most commonly used reliability metric is mean time to failure (MTTF). However, MTTF does not provide information on the reliability characteristics during the typical operational life of a processor, which is usually much shorter than the MTTF. An alternative to MTTF that provides more information to both the designer and the user is the time to failure of a small percentage, say n%, of the population, denoted by tn . Determining tn , however, requires knowledge of the distribution of processor failure times which is generally hard to obtain. In this paper, we show (1) how tn can be obtained and incorporated within previous architecture-level lifetime reliability tools, (2) how tn relates to MTTF using state-of-the-art reliability models, and (3) the impact of using MTTF instead of tn on reliability-aware design. We perform our evaluation using RAMP 2.0, a state-of-the-art architecture-level tool for lifetime reliability measurements. Our analysis shows that no clear relationship between tn and MTTF is apparent across several architectures. Two populations with the same MTTF may have different tn , resulting in a difference in the number of failures in the same operational period. MTTF fails to capture such behavior and can thus be misleading. Further, when designing reliability-aware systems, using improvements in MTTF as a proxy for improvements in tn can lead to poor design choices. Depending on the application and the system, MTTF-driven designs may be over-designed (incurring unnecessary cost or performance overhead) or under-designed (failing to meet the required tn reliability target)

On High-Bandwidth Data Cache Design for Multi-Issue Processors

Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The number of instructions that must be processed (including incorrectly predicted ones) will approach 16 or more per cycle. Since memory operations account for about a third of all instructions executed, these systems will have to support multiple data references per cycle. In this paper, we explore reference stream characteristics to determine how best to meet the need for ever increasing access rates. We identify limitations of existing multiported cache designs and propose a new structure, the Locality-Based Interleaved Cache (LBIC), to exploit the characteristics of the data reference stream while approaching the economy of traditional multi-bank cache design. Experimental results show that the LBIC structure is capable of outperforming current multi-ported approaches. 1. Introduction Improvements in microproc..

Performance Issues in Integrating Temporality-Based Caching with Prefetching

this paper, we present a group of caching strategies and evaluate their performance effectiveness when cache prefetching is merged with temporalitybased design. We show that a careful combination of the two techniques can result in a generous reduction in miss ratio and memory traffic. The rest of this paper is organized as follows. The next two sections present the qualitative and quantitative reasoning behind temporality-based design while section 4 discusses the importance of prefetching. Our proposed integrated techniques are given in section 5. Section 6 presents the performance evaluation, and section 7 concludes this work. 2 Temporality-Based Accessing The concept of a cache structure adapting to program behavior to improve the overall system performance requires serious consideration, especially since all load/store references cannot be viewed equally in terms of behavior in a given cache environment. In a recent study [7], Abraham et al. showed through application code profiling that a very small number of load/store instructions are responsible for causing a disproportionate percentage of cache misses. Their findings provide an important direction for cache management research. Caches derive their efficacy from the exploitation of reference locality in application programs. Two types of locality are distinguishable: spatial and temporal. A program exhibits good spatial locality if adjacent memory locations are referenced close in time, and a good temporal locality if a particular memory location is referenced multiple times in a short time interval. Every program Fig. 1. Venn Diagram of Program Reference Type