CMUT-based volumetric ultrasonic imaging array design for forward looking ICE and IVUS applications

Designing a mechanically flexible catheter based volumetric ultrasonic imaging device for intravascular and intracardiac imaging is challenging due to small transducer area and limited number of cables. With a few parallel channels, synthetic phased array processing is necessary to acquire data from a large number of transducer elements. This increases the data collection time and hence reduces frame rate and causes artifacts due to tissue-transducer motion. Some of these drawbacks can be resolved by different array designs offered by CMUT-on-CMOS approach. We recently implemented a 2.1-mm diameter single chip 10 MHz dual ring CMUT-on-CMOS array for forward looking ICE with 64-transmit and 56-receive elements along with associated electronics. These volumetric arrays have the small element size required by high operating frequencies and achieve sub mm resolution, but the system would be susceptible to motion artifacts. To enable real time imaging with high SNR, we designed novel arrays consisting of multiple defocused annular rings for transmit aperture and a single ring receive array. The annular transmit rings are utilized to act as a high power element by focusing to a virtual ring shaped line behind the aperture. In this case, image reconstruction is performed by only receive beamforming, reducing total required firing steps from 896 to 14 with a trade-off in image resolution. The SNR of system is improved more than 5 dB for the same frequency and frame rate as compared to the dual ring array, which can be utilized to achieve the same resolution by increasing the operating frequency.Publisher's Versio

Rare-earth elements and isotopes (Sr, Nd, O, C) in minerals from the Juquiá carbonatite (Brazil): tracers of a multistage evolution

International audienc

Corrigendum: Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain (vol 12, 891, 2018)

Thakur CS, Molin JL, Cauwenberghs G, et al. Corrigendum: Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain (vol 12, 891, 2018). FRONTIERS IN NEUROSCIENCE. 2019;12: 991

Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain.

Neuromorphic engineering (NE) encompasses a diverse range of approaches to information processing that are inspired by neurobiological systems, and this feature distinguishes neuromorphic systems from conventional computing systems. The brain has evolved over billions of years to solve difficult engineering problems by using efficient, parallel, low-power computation. The goal of NE is to design systems capable of brain-like computation. Numerous large-scale neuromorphic projects have emerged recently. This interdisciplinary field was listed among the top 10 technology breakthroughs of 2014 by the MIT Technology Review and among the top 10 emerging technologies of 2015 by the World Economic Forum. NE has two-way goals: one, a scientific goal to understand the computational properties of biological neural systems by using models implemented in integrated circuits (ICs); second, an engineering goal to exploit the known properties of biological systems to design and implement efficient devices for engineering applications. Building hardware neural emulators can be extremely useful for simulating large-scale neural models to explain how intelligent behavior arises in the brain. The principal advantages of neuromorphic emulators are that they are highly energy efficient, parallel and distributed, and require a small silicon area. Thus, compared to conventional CPUs, these neuromorphic emulators are beneficial in many engineering applications such as for the porting of deep learning algorithms for various recognitions tasks. In this review article, we describe some of the most significant neuromorphic spiking emulators, compare the different architectures and approaches used by them, illustrate their advantages and drawbacks, and highlight the capabilities that each can deliver to neural modelers. This article focuses on the discussion of large-scale emulators and is a continuation of a previous review of various neural and synapse circuits (Indiveri et al., 2011). We also explore applications where these emulators have been used and discuss some of their promising future applications