The role of the Fermi level pinning in gate tunable graphene-semiconductor junctions

Graphene based transistors relying on a conventional structure cannot switch properly because of the absence of an energy gap in graphene. To overcome this limitation, a barristor device was proposed, whose operation is based on the modulation of the graphene-semiconductor (GS) Schottky barrier by means of a top gate, and demonstrating an ON-OFF current ratio up to 10⁵. Such a large number is likely due to the realization of an ultra clean interface with virtually no interface trapped charge. However, it is indeed technologically relevant to know the impact that the interface trapped charges might have on the barristor's electrical properties. We have developed a physics based model of the gate tunable GS heterostructure where non-idealities such as Fermi Level Pinning (FLP) and a "bias dependent barrier lowering effect" has been considered. Using the model we have made a comprehensive study of the barristor's expected digital performance

2D pn junctions driven out-of-equilibrium

The pn junction is a fundamental electrical component in modern electronics and optoelectronics. Currently, there is a great deal of interest in the two-dimensional (2D) pn junction. Although many experiments have demonstrated the working principle, there is a lack of fundamental understanding of its basic properties and expected performances, in particular when the device is driven out-of-equilibrium. To fill the current gap in understanding, we investigate the electrostatics and electronic transport of 2D lateral pn junctions. To do so we implement a physics-based simulator that self-consistently solves the 2D Poisson's equation coupled to the drift-diffusion and continuity equations. Notably, the simulator takes into account the strong influence of the out-of-plane electric field through the surrounding dielectric, capturing the weak screening of charge carriers. Supported by simulations, we propose a Shockley-like equation for the ideal current-voltage (J-V) characteristics, in full analogy to the bulk junction after defining an effective depletion layer (EDL). We also discuss the impact of recombination-generation processes inside the EDL, which actually produce a significant deviation with respect to the ideal behavior, consistently with experimental data. Moreover, we analyze the capacitances and conductance of the 2D lateral pn junction. Based on its equivalent circuit we investigate its cut-off frequency targeting RF applications. To gain deeper insight into the role played by material dimensionality, we benchmark the performances of single-layer MoS2 (2D) lateral pn junctions against those of the Si (3D) junction. Finally, a practical discussion on the short length 2D junction case together with the expected impact of interface states has been provided. Given the available list of 2D materials, this work opens the door to a wider exploration of material-dependent performances

Physical model of the contact resistivity of metal-graphene junctions

While graphene-based technology shows great promise for a variety of electronic applications, including radio-frequency devices, the resistance of the metal-graphene contact is a technological bottleneck for the realization of viable graphene electronics. One of the most important factors in determining the resistance of a metal-graphene junction is the contact resistivity. Despite the large number of experimental works that exist in the literature measuring the contact resistivity, a simple model of it is still lacking. In this paper, we present a comprehensive physical model for the contact resistivity of these junctions, based on the Bardeen Transfer Hamiltonian method. This model unveils the role played by different electrical and physical parameters in determining the specific contact resistivity, such as the chemical potential of interaction, the work metal-graphene function difference, and the insulator thickness between the metal and graphene. In addition, our model reveals that the contact resistivity is strongly dependent on the bias voltage across the metal-graphene junction. This model is applicable to a wide variety of graphene-based electronic devices and thus is useful for understanding how to optimize the contact resistance in these systems

Study and modeling of multi-gate transistors in the context of CMOS technology scaling

L'escalat dels transistors MOSFET convencionals ha portat a aquests dispositius a la nanoescala per incrementar tant les seves prestacions com el nombre de components per xip. En aquest process d'escalat, els coneguts "Short Channel Effects" representen una forta limitació. La forma més efectiva de suprimir aquests efectes i aixi estendre l'ús del MOSFET convencional, és la reducció del gruix de l'òxid de porta i l'augment de la concentració de dopants al canal. Quan el gruix d'òxid de porta es redueix a unes quantes capes atòmiques, apareix l'efecte túnel mecano-quàntic d'electrons, produint un gran augment en els corrents de fuita, perjudicant la normal operació dels MOSFETs. Això ha fet obligatori l'ús de materials d'alta permitivitat o materials high-κ en els dielèctrics de porta. Tot i les solucions proposades, la reducció de les dimensiones físiques del MOSFET convencional no pot ser mantinguda de forma indefinida i per mantenir la tendència tecnològica s'han suggerit noves estructures com ara MOSFETs multi-porta de cos ultra-prim. En particular, el MOSFET de doble porta és considerat com una estructura multi-porta prometedora per les seves diverses qualitats i avantatges en l'escalat. Aquesta tesi s'enfoca en la modelització de dispositius MOSFET de doble porta i, en particular, en la modelització del corrent túnel de porta que afecta críticamente al consum de potència del transistor. Primerament desenvolupem un model quàntic compacte tant per al potencial electrostàtic com per a la càrrega elèctrica en el transistor de doble-porta simètric amb cos no dopat. Després, aquest model quàntic s'utilitza per proposar un model analític compacte per al corrent túnel directe amb SiO2 com dielèctric de porta, primerament, i després amb una doble capa composta de SiO2 com a capa interfacial i un material "high-κ". Finalment se desenvolupa un mètode precís per calcular el corrent túnel de porta. El mètode es basa en l'aplicació de condicions de frontera absorbents i, més especificament, en el mètode PML. Aquesta tesi està motivada per les recomanacions fetes pel "International Technology Roadmap of Semiconductors" (ITRS) sobre la necessitat existent de modelatge i simulació d'estructures semiconductores multi-porta.The scaling of the conventional MOSFETs has led these devices to the nanoscale to increase both the performance and the number of components per chip. In this process, the so-called "Short Channel Effects" have arisen as a limiting factor. To extend the use of the bulk MOSFETs, the most effective ways of suppressing such effects are the reduction of the gate oxide thickness and increasing of the channel doping concentration. When the gate oxide thickness is reduced to a few atomic layers, quantum mechanical tunneling is responsible of a huge increase in the gate leakage current impairing the normal operation of MOSFETs. This has made mandatory the use of high permittivity materials or high-κ as gate dielectrics. Despite the proposed solutions, reduction of the physical dimensions of the conventional MOSFETs cannot be maintained. To keep the technological trend, new MOSFET structures have been suggested such as ultra-thin body Multi-Gate MOSFETs. In particular, the Double-Gate MOSFETs is considered as a promising MG structure for its several qualities and advantages in scaling. This thesis focuses on the modeling of Double-Gate MOSFET and, in particular, on the modeling of the gate leakage current critically affecting the power consumption. First we develop a compact quantum model for both the electrostatic potential and the electric charge in symmetric double-gate MOSFET with undoped thin body. Then, this quantum model is used to propose an analytical compact model for the direct tunnelling current with SiO2 as gate dielectric, firstly, and later assuming a dual layer consisting of a SiO2 interfacial layer and a high-κ material. Finally, an accurate method for the calculation of the gate tunnelling current is developed. It is based on Absorbing Boundary Conditions techniques and, more specifically, on the Perfectly Mached Layer (PML) method. This thesis is motivated by the recommendations given by the "International Technology Roadmap of Semiconductors" (ITRS) about the need for the modeling and simulation of multi-gate semiconductor structures

Impact of graphene polycrystallinity on the performance of graphene field-effect transistors

We have used a multi-scale physics-based model to predict how the grain size and different grain boundary morphologies of polycrystalline graphene will impact the performance metrics of graphene field-effect transistors. We show that polycrystallinity has a negative impact on the transconductance, which translates to a severe degradation of the maximum and cutoff frequencies. On the other hand, polycrystallinity has a positive impact on current saturation, and a negligible effect on the intrinsic gain. These results reveal the complex role played by graphene grain boundaries and can be used to guide the further development and optimization of graphene-based electronic devices

Photoresponse of Graphene-Gated Graphene-GaSe Heterojunction Devices

Altres ajuts: This project has received funding from the European Union's Horinon 2020 research and innovation programme. This work was also partially funded by the Ministerio de Economía y Competitividad. The authors also acknowledge the funding from the Academy of Finland (Grants 276376, 284548, 295777, 304666, 312294, 312297, 312551, and 314810), TEKES-the Finnish Funding Agency for Technology and Innovation. The authors also thank Dr. Stephan Suckow in AMO GmbH for fruitful discussions about photonic device behavior.Because of their extraordinary physical properties, low-dimensional materials including graphene and gallium selenide (GaSe) are promising for future electronic and optoelectronic applications, particularly in transparent-flexible photodetectors. Currently, the photodetectors working at the near-infrared spectral range are highly indispensable in optical communications. However, the current photodetector architectures are typically complex, and it is normally difficult to control the architecture parameters. Here, we report graphene-GaSe heterojunction-based field-effect transistors with broadband photodetection from 730-1550 nm. Chemical-vapor-deposited graphene was employed as transparent gate and contact electrodes with tunable resistance, which enables effective photocurrent generation in the heterojunctions. The photoresponsivity was shown from 10 to 0.05 mA/W in the near-infrared region under the gate control. To understand behavior of the transistor, we analyzed the results via simulation performed using a model for the gate-tunable graphene-semiconductor heterojunction where possible Fermi level pinning effect is considered

Study and Modeling of Multi‐ Gate Transistors in the Context of CMOS Technology Scaling

L’escalat dels transistors MOSFET convencionals ha portat a aquests dispositius a la nanoescala per incrementar tant les seves prestacions com el nombre de components per xip. En aquest process d’escalat, els coneguts “Short Channel Effects” representen una forta limitació. La forma més efectiva de suprimir aquests efectes i aixi estendre l’ús del MOSFET convencional, és la reducció del gruix de l’òxid de porta i l’augment de la concentració de dopants al canal. Quan el gruix d’òxid de porta es redueix a unes quantes capes atòmiques, apareix l’efecte túnel mecano-quàntic d’electrons, produint un gran augment en els corrents de fuita, perjudicant la normal operació dels MOSFETs. Això ha fet obligatori l’ús de materials d’alta permitivitat o materials high-κ en els dielèctrics de porta. Tot i les solucions proposades, la reducció de les dimensiones físiques del MOSFET convencional no pot ser mantinguda de forma indefinida i per mantenir la tendència tecnològica s’han suggerit noves estructures com ara MOSFETs multi-porta de cos ultra-prim. En particular, el MOSFET de doble porta és considerat com una estructura multi-porta prometedora per les seves diverses qualitats i avantatges en l’escalat. Aquesta tesi s’enfoca en la modelització de dispositius MOSFET de doble porta i, en particular, en la modelització del corrent túnel de porta que afecta críticamente al consum de potència del transistor. Primerament desenvolupem un model quàntic compacte tant per al potencial electrostàtic com per a la càrrega elèctrica en el transistor de doble-porta simètric amb cos no dopat. Després, aquest model quàntic s’utilitza per proposar un model analític compacte per al corrent túnel directe amb SiO2 com dielèctric de porta, primerament, i després amb una doble capa composta de SiO2 com a capa interfacial i un material “high-κ”. Finalment se desenvolupa un mètode precís per calcular el corrent túnel de porta. El mètode es basa en l’aplicació de condicions de frontera absorbents i, més especificament, en el mètode PML. Aquesta tesi està motivada per les recomanacions fetes pel “International Technology Roadmap of Semiconductors” (ITRS) sobre la necessitat existent de modelatge i simulació d’estructures semiconductores multi-porta.The scaling of the conventional MOSFETs has led these devices to the nanoscale to increase both the performance and the number of components per chip. In this process, the so-called “Short Channel Effects” have arisen as a limiting factor. To extend the use of the bulk MOSFETs, the most effective ways of suppressing such effects are the reduction of the gate oxide thickness and increasing of the channel doping concentration. When the gate oxide thickness is reduced to a few atomic layers, quantum mechanical tunneling is responsible of a huge increase in the gate leakage current impairing the normal operation of MOSFETs. This has made mandatory the use of high permittivity materials or high-κ as gate dielectrics. Despite the proposed solutions, reduction of the physical dimensions of the conventional MOSFETs cannot be maintained. To keep the technological trend, new MOSFET structures have been suggested such as ultra-thin body Multi-Gate MOSFETs. In particular, the Double-Gate MOSFETs is considered as a promising MG structure for its several qualities and advantages in scaling. This thesis focuses on the modeling of Double-Gate MOSFET and, in particular, on the modeling of the gate leakage current critically affecting the power consumption. First we develop a compact quantum model for both the electrostatic potential and the electric charge in symmetric double-gate MOSFET with undoped thin body. Then, this quantum model is used to propose an analytical compact model for the direct tunnelling current with SiO2 as gate dielectric, firstly, and later assuming a dual layer consisting of a SiO2 interfacial layer and a high-κ material. Finally, an accurate method for the calculation of the gate tunnelling current is developed. It is based on Absorbing Boundary Conditions techniques and, more specifically, on the Perfectly Mached Layer (PML) method. This thesis is motivated by the recommendations given by the “International Technology Roadmap of Semiconductors” (ITRS) about the need for the modeling and simulation of multi-gate semiconductor structures

Dynamical properties of polaritons in semiconductor microcavities

The main aim of the present thesis work is to study the fundamental features of the different relaxation process for polaritons, when the semiconductor micro-cavity is excited by a non-resonantlaser pump. Our numerical simulations of polariton relaxation, clearly demonstrate that, for the experimental situation, the electron-polariton relaxation mechanism is the most efficient, contrary to the recent published theoretical work and confirming the experimental results. In the present work, the polariton-polariton scattering is inefficient due to the low excitation densities.Magíster en FísicaMaestrí

The role of the Fermi level pinning in gate tunable graphene-semiconductor junctions

Graphene based transistors relying on a conventional structure cannot switch properly because of the absence of an energy gap in graphene. To overcome this limitation, a barristor device was proposed, whose operation is based on the modulation of the graphene-semiconductor (GS) Schottky barrier by means of a top gate, and demonstrating an ON-OFF current ratio up to 10⁵. Such a large number is likely due to the realization of an ultra clean interface with virtually no interface trapped charge. However, it is indeed technologically relevant to know the impact that the interface trapped charges might have on the barristor's electrical properties. We have developed a physics based model of the gate tunable GS heterostructure where non-idealities such as Fermi Level Pinning (FLP) and a "bias dependent barrier lowering effect" has been considered. Using the model we have made a comprehensive study of the barristor's expected digital performance

Physical model of the contact resistivity of metal-graphene junctions

While graphene-based technology shows great promise for a variety of electronic applications, including radio-frequency devices, the resistance of the metal-graphene contact is a technological bottleneck for the realization of viable graphene electronics. One of the most important factors in determining the resistance of a metal-graphene junction is the contact resistivity. Despite the large number of experimental works that exist in the literature measuring the contact resistivity, a simple model of it is still lacking. In this paper, we present a comprehensive physical model for the contact resistivity of these junctions, based on the Bardeen Transfer Hamiltonian method. This model unveils the role played by different electrical and physical parameters in determining the specific contact resistivity, such as the chemical potential of interaction, the work metal-graphene function difference, and the insulator thickness between the metal and graphene. In addition, our model reveals that the contact resistivity is strongly dependent on the bias voltage across the metal-graphene junction. This model is applicable to a wide variety of graphene-based electronic devices and thus is useful for understanding how to optimize the contact resistance in these systems