Modeling & Simulation of High Performance Nanoscale MOSFETs

Silicon-on-insulator (SOI) has been the forerunner of the CMOS technology in the last few decades offering superior CMOS devices with higher speed, higher density and reduced second order effects for submicron VLSI applications.A new type of transistor without junctions and no doping concentration gradients is analysed and demonstrated. These device structures address the challenge of short channel effects (SCEs) resulting with scaling of transistor dimensions and higher performance for deep submicron VLSI integration. Recent experimental studies have invigorated interest in partially depleted (PD) SOI devices because of their potentially superior scalability relative to bulk silicon CMOS devices. SELBOX structure offer an alternative way of suppressing kink effect and self heating effects in PD-SOI devices with a proper selection of oxide gap length. Also in order to mitigate the difficulties in fabrication of ultra thin devices for the semiconductor industry, resulting from scaling of gate length in MOSFET, a new device structure called junctionless (JL) transistors have recently been reported as an alternative device. In conclusion, extensive numerical simulation studies were used to explore and compare the electrical characteristics of SELBOX SOI MOSFET with a conventional single-material gate (SMG) bulk MOSFET. The proposed work investigates the DC and AC characteristics of the junctionless transistors. Also the performance analysis of JL transistors is compared and presented with the conventional DG MOSFET structure. The results presented in this work are expected to provide incentive for further experimental exploration

Skybridge: A New Nanoscale 3-D Computing Framework for Future Integrated Circuits

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, continuing the traditional way of scaling to sub-20nm technologies is proving to be very difficult as MOSFETs are reaching their fundamental performance limits [1] and interconnection bottleneck is dominating IC operational power and performance [2]. Migrating to 3-D, as a way to advance scaling, has been elusive due to inherent customization and manufacturing requirements in CMOS architecture that are incompatible with 3-D organization. Partial attempts with die-die [3] and layer-layer [4] stacking have their own limitations [5]. We propose a new 3-D IC fabric technology, Skybridge [6], which offers paradigm shift in technology scaling as well as design. We co-architect Skybridge’s core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D template. Our extensive bottom-up simulations, accounting for detailed material system structures, manufacturing process, device, and circuit parasitics, carried through for several designs including a designed microprocessor, reveal a 30-60x density, 3.5x performance/watt benefits, and 10x reduction in interconnect lengths vs. scaled 16-nm CMOS [6]. Fabric-level heat extraction features are found to be effective in managing IC thermal profiles in 3-D. This 3-D integrated fabric proposal overcomes the current impasse of CMOS in a manner that can be immediately adopted, and offers unique solution to continue technology scaling in the 21st century

Multi-gate Si nanowire MOSFETs:fabrication, strain engineering and transport analysis

Multi-gate devices e.g. gate-all-around (GAA) Si nanowires and FinFETs are promising can- didates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effect and optimized power consumption are the major benefits of such archi- tectures due to higher electrostatic control of the channel. On the other hand, Si nanowires show excellent mechanical properties e.g. yield and fracture strengths of 10±2% and 30±1% in comparison to 3.7% and 4.0% for bulk Si, respectively, a strong motivation to be used as exclusive platforms for innovative nanoelectronic applications e.g. novel strain engineering techniques for carrier transport enhancement in multi-gate 3D suspended channels or lo- cal band-gap modulation using > 4 GPa uniaxial tensile stress in suspended Si channels to enhance the band-to-band tunneling current in multi-gate Tunnel-FETs, all without plastic deformation and therefore, no carrier mobility degradation in deeply scaled channels. In this thesis and as a first step, a precise built-in stress analysis during local thermal oxidation of suspended Si NWs in the presence of a Si3N4 tensile hard mask was done. Accumulation of up to 2.6 GPa uniaxial tensile stress in the buckled NWs is reported. The contribution of hard mask/spacer engineering on the stress level and the NW formation was studied and buckled self-aligned dual NW MOSFETs on bulk Si with two sub-100 nm cross-sectional Si cores including ∼0.8 uniaxial tensile stress are reported. Micro-Raman spectroscopy was widely used in this thesis to measure stress in the buckled NWs on both bulk and SOI substrates. A process flow was designed to make dense array of GAA sub-5 nm cross-sectional Si NWs using a SOI substrate including a high level of stress. The NW stress level can be engineered simply using e.g. metal-gate thin film stress suitable for both NMOS and PMOS devices. Lately, highly and heavily doped architectures with a single-type doping profile from source to drain, called junctionless and accumulation-mode devices, are proposed to significantly simplify the fabrication process, address a few technical limitations e.g. ultra-abrupt junctions in order to fabricate shorter channel length devices. Therefore, in this process flow, a highly doped accumulation-mode was targeted as the operation mechanism. Finally, extensive TCAD device simulation was done on GAA Si NW JL MOSFETs to study the corner effects on the device characteristics, from subthreshold to strong accumulation, report the concept of local volume accumulation/depletion, quantum flat-band voltage, significant bias-dependent series resistance in junctionless MOSFETs and finally, support the experimental data to extract precisely the carrier mobility in sub-5 nm Si NW MOSFETs

Multigate MOSFETs for digital performance and high linearity, and their fabrication techniques

The aggressive downscaling of complementary metal–oxide–semiconductor (CMOS) technology is facing great challenges to overcome severe short-channel effects. Multigate MOSFETs are one of the most promising candidates for scaling beyond Si CMOS, due to better electrostatic control as compared to conventional planar MOSFETs. Conventional dry etching-induced surface damage is one of the main sources of performance degradation for multigate transistors, especially for III-V high mobility materials. It is also challenging to increase the fin aspect ratio by dry etching because of the non-ideal anisotropic etching profile. Here, we report a novel method, inverse metal-assisted chemical etching (i-MacEtch), in lieu of conventional RIE etching, for 3D fin channel formation. InP junctionless FinFETs with record high-aspect-ratio (~ 50:1) fins are demonstrated by this method for the first time. The i-MacEtch process flow eliminates dry-etching-induced plasma damage, high energy ion implantation damage, and high temperature annealing, allowing for the fabrication of InP fin channels with atomically smooth sidewalls. The sidewall features resulting from this unique and simplified process ensure high interface quality between high-k dielectric layer and InP fin channel. Experimental and theoretical analyses show that high-aspect-ratio FinFETs, which could deliver more current per area under much relaxed horizontal geometry requirements, are promising in pushing the technology node ahead where conventional scaling has met its physical limits. The performance of the FinFET was further investigated through numerical simulation. A new kind of FinFET with asymmetric gate and source/drain contacts has been proposed and simulated. By benchmarking with conventional symmetric FinFET, better short-channel behavior with much higher current density is confirmed. The design guidelines are provided. The overall circuit delay can be minimized by optimizing gate lengths according to different local parasites among circuits in interconnection-delay-dominated SoC applications. Continued transistor scaling requires even stronger gate electrostatic control over the channel. The ultimate scaling structure would be gate-all-around nanowire MOSFETs. We demonstrate III-V junctionless gate-all-around (GAA) nanowire (NW) MOSFETs for the first time. For the first time, source/drain (S/D) resistance and thermal budget are minimized by regrowth using metalorganic chemical vapor deposition (MOCVD) in III-V MOSFETs. The fabricated short-channel (Lg=80 nm) GaAs GAA NWFETs with extremely narrow nanowire width (WNW= 9 nm) show excellent transconductance (gm) linearity at biases (300 mV), characterized by the high third intercept point (2.6 dBm). The high linearity is especially important for low power applications because it is insensitive to bias conditions

Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, scaling to sub-20nm technologies is proving to be challenging as MOSFETs are reaching their fundamental limits and interconnection bottleneck is dominating IC operational power and performance. Migrating to 3-D, as a way to advance scaling, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization. Partial attempts with die-die and layer-layer stacking have their own limitations. We propose a 3-D IC fabric technology, Skybridge[TM], which offers paradigm shift in technology scaling as well as design. We co-architect Skybridge's core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D template. Our extensive bottom-up simulations, accounting for detailed material system structures, manufacturing process, device, and circuit parasitics, carried through for several designs including a designed microprocessor, reveal a 30-60x density, 3.5x performance per watt benefits, and 10X reduction in interconnect lengths vs. scaled 16-nm CMOS. Fabric-level heat extraction features are shown to successfully manage IC thermal profiles in 3-D. Skybridge can provide continuous scaling of integrated circuits beyond CMOS in the 21st century.Comment: 53 Page

ANALYTICAL COMPACT MODELING OF NANOSCALE MULTIPLE-GATE MOSFETS.

L’objectiu principal d’aquest treball és el desenvolupament d’un model compacte per a MOSFETs de múltiple porta d’escala nanomètrica, que sigui analític, basat en la física del dispositiu, i predictiu per a simulacions AC i DC. Els dispositius investigats són el MOSFET estàndar en mode d’inversió, a més d’un nou dispositiu anomenat “junctionless MOSFET” (MOSFET sense unions). El model es va desenvolupar en una formulació compacta amb l’ajuda de l’equació de Poisson i la tècnica de la transformación conforme de Schwarz-Cristoffel. Es varen obtenir les equacions del voltatge llindar i el pendent subllindar. Usant la funció W de Lambert, a més d’una funció de suavització per a la transcició entre les regions de depleció i acumulació, s’obté un model unificat de la densitat de càrrega, vàlid per a tots els modes d’operació del transistor. S’estudien també les dependències entre els paràmetres físics del dispositiu i el seu impacte en el seu rendiment. Es tenen en compteefectes importants de canal curt i de quantització. Es discuteixen també la simetria al voltant de Vds= 0 V, i la continuïtat del corrent de drenador en les derivades d’ordre superior. El model va ser validat mitjançant simulacions TCAD numèriques i mesures experimentals.El objetivo principal de este trabajo es el desarrollo de un modelo compacto para MOSFETs de múltiple puerta de escala nanométrica, que sea analítico, basado en la física del dispositivo, y predictivo para simulaciones AC y DC. Los dispositivos investigados son el MOSFET estándar en modo inversión, además de un nuevo dispositivo llamado “junctionless MOSFET” (MOSFET sin uniones). El modelo se desarrolló en una formulación compacta con la ayuda de la ecuación de Poisson y la técnica de transformación conforme de Schwarz-Cristoffel. Se obtuvieron las ecuaciones del voltaje umbral y la pendiente subumbral. Usando la función W de Lambert, además de una función de suavización para la transición entre las regiones de depleción y acumulación, se obtiene un modelo unificado de la densidad de carga, válido para todos los modos de operación del transistor. Se estudian también las dependencias entre los parámetros físicos del dispositivo y su impacto en su rendimiento. Se tienen en cuenta efectos importantes de canal corto y de cuantización. Se discuten también la simetría alrededor de Vds= 0 V, y la continuidad de la corriente de drenador en las derivadas de orden superior. El modelo fue validado mediante simulaciones TCAD numéricas y medidas experimentales.The main focus is on the development of an analytical, physics-based and predictive DC and AC compact model for nanoscale multiple-gate MOSFETs. The investigated devices are the standard inversion mode MOSFET and a new device concept called junctionless MOSFET. The model is derived in closed-from with the help of Poisson's equation and the conformal mapping technique by Schwarz-Christoffel. Equations for the calculation of the threshold voltage and subthreshold slope are derived. Using Lambert's W-function and a smoothing function for the transition between the depletion and accumulation region, an unified charge density model valid for all operating regimes is developed. Dependencies between the physical device parameters and their impact on the device performance are worked out. Important short-channel and quantization effects are taken into account. Symmetry around Vds = 0 V and continuity of the drain current at derivatives of higher order are discussed. The model is validated versus numerical TCAD simulations and measurement data

A study of silicon and germanium junctionless transistors

Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V

Transport properties and low-frequency noise in low-dimensional structures

Les propriétés électriques et physiques de structures à faible dimensionalité ont été étudiées pour des applications dans des domaines divers comme l électronique, les capteurs. La mesure du bruit bruit à basse fréquence est un outil très utile pour obtenir des informations relatives à la dynamique des porteurs, au piègeage des charges ou aux mécanismes de collision. Dans cette thèse, le transport électronique et le bruit basse fréquence mesurés dans des structures à faible dimensionnalité comme les dispositifs multi-grilles (FinFET, JLT ), les nanofils 3D en Si/SiGe, les nanotubes de carbone ou à base de graphène sont présentés. Pour les approches top-down et bottom-up , l impact du bruit est analysé en fonction de la dimensionalité, du type de conduction (volume vs surface), de la contrainte mécanique et de la présence de jonction metal-semiconducteur.Electrical and physical properties of low-dimensional structures have been studied for the various applications such as electronics, sensors, and etc. Low-frequency noise measurement is also a useful technique to give more information for the carrier dynamics correlated to the oxide traps, channel defects, and scattering. In this thesis, the electrical transport and low-frequency noise of low-dimensional structure devices such as multi-gate structures (e.g. FinFETs and Junctionless FETs), 3-D stacked Si/SiGe nanowire FETs, carbon nanotubes, and graphene are presented. From the view point of top-down and bottom-up approaches, the impacts of LF noise are investigated according to the dimensionality, conduction mechanism (surface or volume conduction), strain technique, and metal-semiconductor junctions.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Novel III-V compound semiconductor technologies for low power digital logic applications

As silicon (Si) complementary metal oxide semiconductor (CMOS) technology continues to scale into the 10 nm node, chip power consumption is approaching 200 W/cm2 and any further increase is unsustainable. Incorporating III-V compound semiconductor n-type devices into future CMOS generations could allow for the the reduction in supply voltage, and therefore, power consumption, while simultaneously improving on-state performance. The advanced state of Si CMOS places stringent demands on III-V devices, however: the current 14 nm Si tri-gate devices employ high aspect ratio, densely spaced fins which serve to significantly increase current per chip surface area. III-V devices need to significantly out perform state of the art Si devices in order to merit their disruptive incorporation into the well established CMOS process. This necessitates that they too exploit the vertical dimension. To this end, this thesis reports on the fabrication, measurement and analysis of high aspect ratio junctionless InGaAs FinFETs. The junctionless architecture was first demonstrated in 2010 and was shown to circumvent pro- hibitive fabrication challenges for devices with ultra short gate lengths. This work investigated the impact of fin width on both the on and off-state performance of 200 nm gate length devices, with nominal fin widths of 10, 15 and 20 nm. Excellent subthreshold performance was demonstrated, with the narrowest fin width exhibiting a minimum subthreshold swing (SS) of 73 mV/Dec., and an average SS of 80 mV/Dec. over two decades of current. A maximum on-current, Ion, of 80.51 μA/cm2 was measured at a gate overdrive of 0.5 V from an off-state current, Ioff, of 100 nA/cm2 and a drain voltage, Vd, of 0.5 V, with current normalised by gated perimeter. This is competitive with other III-V junctionless devices at similar gate lengths. With current normalised to base fin width, however, Ion increases to 371.8 μA/cm2, which is a record value among equivalently normalised non-planar III-V junctionless devices at any gate length. This technology, therefore, clearly demonstrates the feasibility of incorporating scaled, etched InGaAs fins into future logic generations. Perhaps the greatest bottleneck to the incorporation of III-V compounds into future CMOS technology nodes, however, is the lack of a suitable III-V PMOS candidate: co-integrating different material systems onto a common substate incurs great fabrication complexity, and therefore, cost. III-V antimonides, however, have recently emerged as promising candidates for III-V PMOS and exhibit the highest bulk electron mobility of all III-Vs in addition to a hole mobility second only to germanium. InGaSb ternary compounds have been shown to offer the best combined performance for electrons and holes in the same material, and as such, have the potential to the enable the most simplistic incarnation of III-V CMOS; provided, of course, that is possible to form a gate stack to both device polarities with sufficient electrical properties. To date, however, there has been no investigation into the high-k dielectric interface to InGaSb. To this end, this thesis presents results of the first investigation into the impact of in-situ H2 plasma exposure on the electrical properties of the p/n-In0.3Ga0.7Sb-Al2O3 interface. The parameter space was explored systematically in terms of H2 plasma power and exposure time, and further, the impact of impact of in-situ trimethylaluminium (TMA) pre-cleaning and annealing in forming gas was assessed. Metal oxide semiconductor capacitors (MOSCAPs) were fabricated subsequent to H2 plasma processing and Al2O3 deposition, and the correspond- ing capacitance-voltage and conductance-voltage measurements were analysed both qualita- tively and quantitatively via the simulation of an equivalent circuit model. X-Ray photoelectron spectroscopy (XPS) analysis of samples processed as part of the plasma power series revealed a combination of ex-situ HCl cleaning and in-situ H2 plasma exposure to completely remove In and Sb sub oxides, with the Ga-O content reduced to Ga-O:InGaSb <0.1. The optimal process, which included ex-situ HCl surface cleaning, in-situ H2 plasma and TMA pre-cleaning, and a post gate metal forming gas anneal, was unequivocally demonstrated to yield a fully unpinnned MOS interface with both n and p-type MOSCAPs explicitly demonstrating a genuine minority carrier response. Interface state and border trap densities were extracted, with a minimum Dit of 1.73x1012 cm-2 eV-1 located at ~110 meV below the conduction band edge and peak border trap densities approximately aligned with the valence and conduction band edges of 3x1019 cm-3 eV-1 and 6.5x1019 cm-3 eV-1 respectively. These results indicate that the optimal gate stack process is indeed applicable to both p and n- type InGaSb MOSFETs, and therefore, represent a critical advancement towards achieving high performance III-V CMOS

Caractérisation électrique et modélisation du transport dans matériaux et dispositifs SOI avancés

This thesis is dedicated to the electrical characterization and transport modeling in advanced SOImaterials and devices for ultimate micro-nano-electronics. SOI technology is an efficient solution tothe technical challenges facing further downscaling and integration. Our goal was to developappropriate characterization methods and determine the key parameters. Firstly, the conventionalpseudo-MOSFET characterization was extended to heavily-doped SOI wafers and an adapted modelfor parameters extraction was proposed. We developed a nondestructive electrical method to estimatethe quality of bonding interface in metal-bonded wafers for 3D integration. In ultra-thin fully-depletedSOI MOSFETs, we evidenced the parasitic bipolar effect induced by band-to-band tunneling, andproposed new methods to extract the bipolar gain. We investigated multiple-gate transistors byfocusing on the coupling effect in inversion-mode vertical double-gate SOI FinFETs. An analyticalmodel was proposed and subsequently adapted to the full depletion region of junctionless SOI FinFETs.We also proposed a compact model of carrier profile and adequate parameter extraction techniques forjunctionless nanowires.Cette thèse est consacrée à la caractérisation et la modélisation du transport électronique dans des matériaux et dispositifs SOI avancés pour la microélectronique. Tous les matériaux innovants étudiés(ex: SOI fortement dopé, plaques obtenues par collage etc.) et les dispositifs SOI sont des solutions possibles aux défis technologiques liés à la réduction de taille et à l'intégration. Dans ce contexte,l'extraction des paramètres électriques clés, comme la mobilité, la tension de seuil et les courants de fuite est importante. Tout d'abord, la caractérisation classique pseudo-MOSFET a été étendue aux plaques SOI fortement dopées et un modèle adapté pour l'extraction de paramètres a été proposé. Nous avons également développé une méthode électrique pour estimer la qualité de l'interface de collage pour des plaquettes métalliques. Nous avons montré l'effet bipolaire parasite dans des MOSFET SOI totalement désertés. Il est induit par l’effet tunnel bande-à-bande et peut être entièrement supprimé par une polarisation arrière. Sur cette base, une nouvelle méthode a été développée pour extraire le gain bipolaire. Enfin, nous avons étudié l'effet de couplage dans le FinFET SOI double grille, en mode d’inversion. Un modèle analytique a été proposé et a été ensuite adapté aux FinFETs sans jonction(junctionless). Nous avons mis au point un modèle compact pour le profil des porteurs et des techniques d’extraction de paramètres