A Double-Sided Stack Low-Inductance Wire-Bondless SiC Power Module with a Ceramic Interposer

The objective of this dissertation research is to develop a novel three-dimensional (3-D) wire bondless power module package for silicon carbide (SiC) power devices to achieve a low parasitic inductance and an improved thermal performance. A half-bridge module consisting of 900-V SiC MOSFETs is realized to minimize stray parasitic inductance as well as to provide both vertical and horizontal cooling paths to maximize heat dissipation. The proposed 3-D power module package was designed, simulated, fabricated and tested. In this module, low temperature co-fired ceramic (LTCC) substrate with vias is utilized as an interposer of which both top and bottom sides are used as die attachment surfaces, the SiC MOSFET bare dies are flip-chip attached on the LTCC interposer using nickel-plated copper balls, high horizontally thermal conductive material is integrated into the LTCC interposer to improve its thermal dissipation capability. Hence, the LTCC interposer provides both electrical and thermal routing and the nickel-plated copper balls replace bond wires in conventional planar power module as the electrical interconnections for the SiC power devices. On the other side, direct bond copper (DBC) substrate are used at both top and bottom sides of the 3-D module to achieve electrical path for SiC devices and double-sided cooling. As a result, 3D power routing is achieved to reduce stray inductance, and both vertical and lateral paths are utilized to spread heat generated by the power devices in this compact module architecture. Electrical simulation was performed to extract the parasitic inductances in the 3-D package and compared to other reported module packages. Low loop parasitic inductance of 4.5nH at a frequency of 1MHz is achieved after optimization. Thermal and thermo-mechanical simulations were also conducted to evaluate the thermal performance and mechanical stress of the proposed module structure. The fabrication process flow of the 3-D wire bondless module is developed and presented. The fabricated half-bridge module was evaluated experimentally by double-pulse test and thermal cycling test. Significant reduction in voltage overshoot and ringing was observed during the double-pulse test, and the module shows no degradation after thermal cycling test. To push the double-sided wire-bondless module to higher voltage application, a 3.3-kV SiC double-sided wire-bondless common source module was designed, fabricated, and tested. Electric field simulations were performed considering the associated challenge of increased electric field strength in the higher-voltage wire-bondless module. High voltage blocking test was added to evaluate the high voltage operation capability as well

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

Integrated silicon photonic packaging

Silicon photonics has garnered plenty of interests from both the academia and industry due to its high-speed transmission potential as well as sensing capability to complement silicon electronics. This has led to significant growth on the former, valuing at US$626.8M in 2017 and is expected to grow 3-fold to US$ 1,988.2M by 2023, based on data from MarketsandMarkets™. Silicon photonics’ huge potential has led to worldwide attention on fundamental research, photonic circuit designs and device fabrication technologies. However, as with silicon electronics in its early years, the silicon photonics industry today is extremely fragmented with various chip designs and layouts. Most silicon photonic devices fabricated are not able to reach the hand of consumers, due to a lack of information related to packaging design rules, components and processes. The importance of packaging technologies, which play a crucial role in turning photonic circuits and devices into the final product that end users can used in their daily lives, has been overlooked and understudied. This thesis aims to – 1. fill the missing gap by adapting existing electronics packaging techniques, 2. assess its scalability, 3. assess supply chain integration and finally 4. develop unique packaging approaches specifically for silicon photonics. The first section focused on high density packaging components and processes using University of California, Berkeley’s state-of-the-art silicon photonic MEMS optical switches as test devices. Three test vehicles were developed using (1) via-less ceramic and (2) spring-contacted electrical interposers for 2D integration and (3) through-glass-via electrical interposers for 2.5D heterogeneous integration. A high density (1) lidless fibre array and (2) a 2D optical interposer, which allows pitch-reduction of optical waveguides were also developed in this thesis. Together, these components demonstrated the world’s first silicon 2 photonic MEMS optical switch package and subsequently the highest density silicon photonic packaging components with 512 electrical I/Os and 272 optical I/Os. The second section then moved away from active optical coupling that was used in the former, investigating instead passive optical packaging concepts for the future. Two approaches were investigated - (1) grating-to-grating and (2) evanescent couplings. The former allows the development of pluggable packages, separating fibre coupling away from the device while the latter allows simultaneous optical and electrical packaging on a glass wafer in a single process. Lastly, the knowhow and concepts developed in this thesis were compiled into packaging design rules and subsequently introduced into H2020-MORPHIC, PIXAPP packaging training courses (as a trainer) and other packaging projects within the group

Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology

Book of Knowledge (BOK) for NASA Electronic Packaging Roadmap

The objective of this document is to update the NASA roadmap on packaging technologies (initially released in 2007) and to present the current trends toward further reducing size and increasing functionality. Due to the breadth of work being performed in the area of microelectronics packaging, this report presents only a number of key packaging technologies detailed in three industry roadmaps for conventional microelectronics and a more recently introduced roadmap for organic and printed electronics applications. The topics for each category were down-selected by reviewing the 2012 reports of the International Technology Roadmap for Semiconductor (ITRS), the 2013 roadmap reports of the International Electronics Manufacturing Initiative (iNEMI), the 2013 roadmap of association connecting electronics industry (IPC), the Organic Printed Electronics Association (OE-A). The report also summarizes the results of numerous articles and websites specifically discussing the trends in microelectronics packaging technologies

Compliant copper microwire arrays for reliable interconnections between large low-CTE packages and printed wiring board

The trend to high I/O density, performance and miniaturization at low cost is driving the industry towards shrinking interposer design rules, requiring a new set of packaging technologies. Low-CTE packages from silicon, glass and low-CTE organic substrates enable high interconnection density, high reliability and integration of system components. However, the large CTE mismatch between the package and the board presents reliability challenges for the board-level interconnections. Novel stress-relief structures that can meet reliability requirements along with electrical performance while meeting the cost constraints are needed to address these challenges. This thesis focuses on a comprehensive methodology starting with modeling, design, fabrication and characterization to validate such stress-relief structures. This study specifically explores SMT-compatible stress-relief microwire arrays in thin polymer carriers as a unique and low-cost solution for reliable board-level interconnections between large low-CTE packages and printed wiring boards. The microwire arrays are pre-fabricated in ultra-thin carriers using low-cost manufacturing processes such as laser vias and copper electroplating, which are then assembled in between the interposer and printed wiring board (PWB) as stress-relief interlayers. The microwire array results in dramatic reduction in solder stresses and strains, even with larger interposer sizes (20 mm × 20 mm), at finer pitch (400 microns), without the need for underfill. The parallel wire arrays result in low resistance and inductance, and therefore do not degrade the electrical performance. The scalability of the structures and the unique processes, from micro to nanowires, provides extendibility to finer pitch and larger package sizes. Finite element method (FEM) was used to study the reliability of the interconnections to provide guidelines for the test vehicle design. The models were built in 2.5D geometries to study the reliability of 400 µm-pitch interconnections with a 100 µm thick, 20 mm × 20 mm silicon package that was SMT-assembled onto an organic printed wiring board. The performance of the microwire array interconnection is compared to that of ball grid array (BGA) interconnections, in warpage, equivalent plastic strain and projected fatigue life. A unique set of materials and processes was used to demonstrate the low-cost fabrication of microwire arrays. Copper microwires with 12 µm diameter and 50 µm height were fabricated on both sides of a 50 µm thick, thermoplastic polymer carrier using dryfilm based photolithography and bottom-up electrolytic plating. The copper microwire interconnections were assembled between silicon interposer and FR-4 PWB through SMT-compatible process. Thermal mechanical reliability of the interconnections was characterized by thermal cycling test from -40°C to 125°C. The initial fatigue failure in the interconnections was identified at 700 cycles in the solder on the silicon package side, which is consistent with the modeling results. This study therefore demonstrated a highly-reliable and SMT-compatible solution for board-level interconnections between large low-CTE packages and printed wiring board.Ph.D

Thermal Isolation of High Power Devices in Heterogeneous Integration

Heterogeneous integration (HI) technologies present an important development in the pursuit of higher performance and reduced size, weight, power and cost of electronic systems (SWAP-C). HI systems, however, pose additional challenges for thermal management due to the disparate operating conditions of the devices. If the thermal coupling between devices can be reduced through a strategy of thermal isolation, then the SWAP-C of the accompanying thermal solution can also be reduced. This is in contrast to the alternative scenario of cooling the entire package to the maximum reliable temperature of the most sensitive devices. This isolation strategy must be implemented without a significant increase in device interconnect distances. A counter-intuitive approach is to seek packaging materials of low thermal conductivity – e.g. glass – and enhance them with arrays of metallic through-layer vias. This dissertation describes the first ever demonstration of integrating such via-enhanced interposers with microfluidic cooling, a thermal solution key to the high power applications for which HI was developed. Among the interposers tested, the best performing were shown to exhibit lower thermal coupling than bulk silicon in selective regions, validating their ability to provide thermal isolation. In the course of the study, the via-enhanced interposer is modeled as a thermal metamaterial with desirable, highly-anisotropic properties. Missing from the supporting literature is an accurate treatment of these interposers under such novel environments as microfluidic cooling. This dissertation identifies a new phenomenon, thermal microspreading, which governs how heat couples into a conductive via array from its surroundings. Both finite element analysis (FEA) and a new analytic solution of the associated boundary value problem (BVP) are used to develop a model for describing microspreading. This improves the ability to correctly predict the thermal behavior of via-enhanced interposers under diverse conditions

MICROELECTRONICS PACKAGING TECHNOLOGY ROADMAPS, ASSEMBLY RELIABILITY, AND PROGNOSTICS

This paper reviews the industry roadmaps on commercial-off-the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due tothe breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down-selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC). The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA). The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN), a data-driven PHM, was discussed in details. Finally, it presented inter- and extra-polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies