Power Analysis and Optimization Techniques for Energy Efficient Computer Systems

Reducing power consumption has become a major challenge in the design and operation of to-day’s computer systems. This chapter describes different techniques addressing this challenge at different levels of system hardware, such as CPU, memory, and internal interconnection network, as well as at different levels of software components, such as compiler, operating system and user applications. These techniques can be broadly categorized into two types: Design time power analysis versus run-time dynamic power management. Mechanisms in the first category use ana-lytical energy models that are integrated into existing simulators to measure the system’s power consumption and thus help engineers to test power-conscious hardware and software during de-sign time. On the other hand, dynamic power management techniques are applied during run-time, and are used to monitor system workload and adapt the system’s behavior dynamically to save energy

Formal Specification and Design Techniques for Wireless Sensor and Actuator Networks

A current trend in the development and implementation of industrial applications is to use wireless networks to communicate the system nodes, mainly to increase application flexibility, reliability and portability, as well as to reduce the implementation cost. However, the nondeterministic and concurrent behavior of distributed systems makes their analysis and design complex, often resulting in less than satisfactory performance in simulation and test bed scenarios, which is caused by using imprecise models to analyze, validate and design these systems. Moreover, there are some simulation platforms that do not support these models. This paper presents a design and validation method for Wireless Sensor and Actuator Networks (WSAN) which is supported on a minimal set of wireless components represented in Colored Petri Nets (CPN). In summary, the model presented allows users to verify the design properties and structural behavior of the system

Dynamic voltage scaling algorithms for soft and hard real-time system

Dynamic Voltage Scaling (DVS) has not been investigated completely for further minimizing the energy consumption of microprocessor and prolonging the operational life of real-time systems. In this dissertation, the workload prediction based DVS and the offline convex optimization based DVS for soft and hard real-time systems are investigated, respectively. The proposed algorithms of soft and hard real-time systems are implemented on a small scaled wireless sensor network (WSN) and a simulation model, respectively

Design and Analysis of an Adaptive Asynchronous System Architecture for Energy Efficiency

Power has become a critical design parameter for digital CMOS integrated circuits. With performance still garnering much concern, a central idea has emerged: minimizing power consumption while maintaining performance. The use of dynamic voltage scaling (DVS) with parallelism has shown to be an effective way of saving power while maintaining performance. However, the potency of DVS and parallelism in traditional, clocked synchronous systems is limited because of the strict timing requirements such systems must comply with. Delay-insensitive (DI) asynchronous systems have the potential to benefit more from these techniques due to their flexible timing requirements and high modularity. This dissertation presents the design and analysis of a real-time adaptive DVS architecture for paralleled Multi-Threshold NULL Convention Logic (MTNCL) systems. Results show that energy-efficient systems with low area overhead can be created using this approach

Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

Resource management algorithms for real-time wireless sensor networks with applications in cyber-physical systems

Wireless Sensor Networks (WSN) are playing a key role in the efficient operation of Cyber Physical Systems (CPS). They provide cost efficient solutions to current and future CPS re- quirements such as real-time structural awareness, faster event localization, cost reduction due to condition based maintenance rather than periodic maintenance, increased opportunities for real-time preventive or corrective control action and fine grained diagnostic analysis. However, there are several critical challenges in the real world applicability of WSN. The low power, low data rate characteristics of WSNs coupled with constraints such as application specified latency and wireless interference present challenges to their efficient integration in CPSs. The existing state of the art solutions lack methods to address these challenges that impediment the easy integration of WSN in CPS. This dissertation develops efficient resource management algorithms enabling WSNs to perform reliable, real-time, cost efficient monitoring. This research addresses three important problems in resource management in the presence of different constraints such as latency, precedence and wireless interference constraints. Additionally, the dissertation proposes a solution to deploy WSNs based real-time monitoring of critical infrastructure such as electrical overhead transmission lines. Firstly, design and analysis of an energy-aware scheduling algorithm encompassing both computation and communication subsystems in the presence of deadline, precedence and in- terference constraints is presented. The energy-delay tradeoff presented by the energy saving technologies such as Dynamic Voltage Scaling (DVS) and Dynamic modulation Scaling (DMS) is studied and methods to leverage it by way of efficient schedule construction is proposed. Performance results show that the proposed polynomial-time heuristic scheduling algorithm offers comparable energy savings to that of the analytically derived optimal solution. Secondly, design, analysis and evaluation of adaptive online algorithms leveraging run- time variations is presented. Specifically, two widely used medium access control schemes are considered and online algorithms are proposed for each. For one, temporal correlation in sensor measurements is exploited and three heuristics with varying complexities are proposed to perform energy minimization using DMS. For another, an adaptive algorithm is proposed addressing channel and load conditions at a node by influencing the selection of either low energy or low delay transmission option. In both cases, the simulation results show that the proposed schemes provide much better energy savings as compared to the existing algorithms. The third component presents design and evaluation of a WSN based framework to mon- itor a CPS namely, electrical overhead transmission line infrastructure. The cost optimized hybrid hierarchical network architecture is composed of a combination of wired, wireless and cellular technologies. The proposed formulation is generic and addresses constraints such as bandwidth and latency; and real world scenarios such as asymmetric sensor data generation, unreliable wireless link behavior, non-uniform cellular coverage and is suitable for cost minimized incremental future deployment. In conclusion, this dissertation addresses several challenging research questions in the area of resource management in WSNs and their applicability in future CPSs through associated algorithms and analyses. The proposed research opens up new avenues for future research such as energy management through network coding and fault diagnosis for reliable monitoring

Performance Analysis of Live-Virtual-Constructive and Distributed Virtual Simulations: Defining Requirements in Terms of Temporal Consistency

This research extends the knowledge of live-virtual-constructive (LVC) and distributed virtual simulations (DVS) through a detailed analysis and characterization of their underlying computing architecture. LVCs are characterized as a set of asynchronous simulation applications each serving as both producers and consumers of shared state data. In terms of data aging characteristics, LVCs are found to be first-order linear systems. System performance is quantified via two opposing factors; the consistency of the distributed state space, and the response time or interaction quality of the autonomous simulation applications. A framework is developed that defines temporal data consistency requirements such that the objectives of the simulation are satisfied. Additionally, to develop simulations that reliably execute in real-time and accurately model hierarchical systems, two real-time design patterns are developed: a tailored version of the model-view-controller architecture pattern along with a companion Component pattern. Together they provide a basis for hierarchical simulation models, graphical displays, and network I/O in a real-time environment. For both LVCs and DVSs the relationship between consistency and interactivity is established by mapping threads created by a simulation application to factors that control both interactivity and shared state consistency throughout a distributed environment

Chapter One – An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques

Power dissipation and energy consumption became the primary design constraint for almost all computer systems in the last 15 years. Both computer architects and circuit designers intent to reduce power and energy (without a performance degradation) at all design levels, as it is currently the main obstacle to continue with further scaling according to Moore's law. The aim of this survey is to provide a comprehensive overview of power- and energy-efficient “state-of-the-art” techniques. We classify techniques by component where they apply to, which is the most natural way from a designer point of view. We further divide the techniques by the component of power/energy they optimize (static or dynamic), covering in that way complete low-power design flow at the architectural level. At the end, we conclude that only a holistic approach that assumes optimizations at all design levels can lead to significant savings.Peer ReviewedPostprint (published version

Asynchronous Data Processing Platforms for Energy Efficiency, Performance, and Scalability

The global technology revolution is changing the integrated circuit industry from the one driven by performance to the one driven by energy, scalability and more-balanced design goals. Without clock-related issues, asynchronous circuits enable further design tradeoffs and in operation adaptive adjustments for energy efficiency. This dissertation work presents the design methodology of the asynchronous circuit using NULL Convention Logic (NCL) and multi-threshold CMOS techniques for energy efficiency and throughput optimization in digital signal processing circuits. Parallel homogeneous and heterogeneous platforms implementing adaptive dynamic voltage scaling (DVS) based on the observation of system fullness and workload prediction are developed for balanced control of the performance and energy efficiency. Datapath control logic with NULL Cycle Reduction (NCR) and arbitration network are incorporated in the heterogeneous platform for large scale cascading. The platforms have been integrated with the data processing units using the IBM 130 nm 8RF process and fabricated using the MITLL 90 nm FDSOI process. Simulation and physical testing results show the energy efficiency advantage of asynchronous designs and the effective of the adaptive DVS mechanism in balancing the energy and performance in both platforms