DESIGN OF NOVEL MULTIPLEXER CIRCUITS IN QCA NANOCOMPUTING

Quantum-dot Cellular Automata (QCA) technology is a promising alternative nano-scale technology for CMOS technology. In digital circuits, a multiplexer is one of the most important components. In this study, an efficient and single layer 2 to 1 QCA multiplexer circuit is proposed using majority gate and inverter gate. In addition, efficient 4 to 1 and 8 to 1 QCA multiplexer circuits are implemented using this 2 to 1 multiplexer circuit. The developed multiplexer circuits are implemented in QCADesigner tool. According to the results, the developed 2 to 1, 4 to 1, and 8 to 1 multiplexer circuits utilize 16 (0.01μm2), 96 (0.11μm2), and 286 (0.43μm2) QCA cell (area). The results demonstrate that the proposed 8 to 1 multiplexer circuit reduces the cost by about 25%-99% compared to the existing multiplexer circuits

An Ultra-Energy-Efficient Reversible Quantum-Dot Cellular Automata 8:1 Multiplexer Circuit

Energy efficiency considerations in terms of reduced power dissipation are a significant issue in the design of digital circuits for very large-scale integration (VLSI) systems. Quantum-dot cellular automata (QCA) is an emerging ultralow power dissipation approach, distinct from traditional, complementary metal-oxide semiconductor (CMOS) technology, for building digital computing circuits. Developing fully reversible QCA circuits has the potential to significantly reduce energy dissipation. Multiplexers are fundamental elements in the construction of useful digital circuits. In this paper, a novel, multilayer, fully reversible QCA 8:1 multiplexer circuit with ultralow energy dissipation is introduced. The power dissipation of the proposed multiplexer is simulated using the QCADesigner-E version 2.2 tool, describing the microscopic physical mechanisms underlying the QCA operation. The results show that the proposed reversible QCA 8:1 multiplexer consumes 89% less energy than the most energy-efficient 8:1 multiplexer circuit previously presented in the literature

NOVEL SINGLE LAYER FAULT TOLERANCE RCA CONSTRUCTION FOR QCA TECHNOLOGY

Quantum-dot Cellular Automata (QCA) technology has become a promising and accessible candidate that can be used for digital circuits implementation at Nanoscale, but the circuit design in the QCA technology has been limited due to fabrication high-defect rate. So, this issue is an interesting research topic in the QCA circuits design. In this study, a novel 3-input Fault Tolerance (FT) Majority Gate (MG) is developed. Accordingly, an efficient 1-bit QCA full adder is developed using the developed 3-input MG. Then, a new 4-bit FT QCA Ripple Carry Adder (RCA) is developed based on the proposed 1-bit FT QCA FA. The developed circuits are implemented in the QCADesigner tool version 2.0.3. The results indicate that the developed QCA circuits provide advantages compared to other QCA circuits in terms of double and single cell missing defect, area and delay time

Quantum-dot Cellular Automata: Review Paper

Quantum-dot Cellular Automata (QCA) is one of the most important discoveries that will be the successful alternative for CMOS technology in the near future. An important feature of this technique, which has attracted the attention of many researchers, is that it is characterized by its low energy consumption, high speed and small size compared with CMOS.  Inverter and majority gate are the basic building blocks for QCA circuits where it can design the most logical circuit using these gates with help of QCA wire. Due to the lack of availability of review papers, this paper will be a destination for many people who are interested in the QCA field and to know how it works and why it had taken lots of attention recentl

An Ultra-Energy-Efficient Reversible Quantum-Dot Cellular Automata 8:1 Multiplexer Circuit

Energy efficiency considerations in terms of reduced power dissipation are a significant issue in the design of digital circuits for very large-scale integration (VLSI) systems. Quantum-dot cellular automata (QCA) is an emerging ultralow power dissipation approach, distinct from traditional, complementary metal-oxide semiconductor (CMOS) technology, for building digital computing circuits. Developing fully reversible QCA circuits has the potential to significantly reduce energy dissipation. Multiplexers are fundamental elements in the construction of useful digital circuits. In this paper, a novel, multilayer, fully reversible QCA 8:1 multiplexer circuit with ultralow energy dissipation is introduced. The power dissipation of the proposed multiplexer is simulated using the QCADesigner-E version 2.2 tool, describing the microscopic physical mechanisms underlying the QCA operation. The results show that the proposed reversible QCA 8:1 multiplexer consumes 89% less energy than the most energy-efficient 8:1 multiplexer circuit previously presented in the literature

Design and simulation of a new QCA-based low-power universal gate

Quantum-dot Cellular Automata (QCA) is recognized in electronics for its low power consumption and high-density capabilities, emerging as a potential substitute for CMOS technology. GDI (Gate Diffusion Input) technology is featured as an innovative approach for enhancing power efficiency and spatial optimization in digital circuits. This study introduces an advanced four-input Improved Gate Diffusion Input (IGDI) design specifically for QCA technology as a universal gate. A key feature of the proposed 10-cell block is the absence of cross-wiring, which significantly enhances the circuit’s operational efficiency. Its universal cell nature allows for the carrying out of various logical gates by merely altering input values, without necessitating any structural redesign. The proposed design showcases notable advancements over prior models, including a reduced cell count by 17%, a 29% decrease in total energy usage, and a 44% reduction in average energy loss. This innovative IGDI design efficiently executes 21 combinational and various sequential functions. Simulations in 18 nm technology, accompanied by energy consumption analyses, demonstrate this design’s superior performance compared to existing models in key areas such as multiplexers, comparators, and memory circuits, alongside a significant reduction in cell count

Reversible Quantum-Dot Cellular Automata-Based Arithmetic Logic Unit

Quantum-dot cellular automata (QCA) are a promising nanoscale computing technology that exploits the quantum mechanical tunneling of electrons between quantum dots in a cell andelectrostatic interaction between dots in neighboring cells. QCA can achieve higher speed, lowerpower, and smaller areas than conventional, complementary metal-oxide semiconductor (CMOS) technology. Developing QCA circuits in a logically and physically reversible manner can provide exceptional reductions in energy dissipation. The main challenge is to maintain reversibility down to the physical level. A crucial component of a computer’s central processing unit (CPU) is the arithmetic logic unit (ALU), which executes multiple logical and arithmetic functions on the data processed by the CPU. Current QCA ALU designs are either irreversible or logically reversible; however, they lack physical reversibility, a crucial requirement to increase energy efficiency. This paper shows a new multilayer design for a QCA ALU that can carry out 16 different operations and is both logically and physically reversible. The design is based on reversible majority gates, which are the key building blocks. We use QCA Designer-E software to simulate and evaluate energy dissipation. The proposed logically and physically reversible QCA ALU offers an improvement of 88.8% in energy efficiency. Compared to the next most efficient 16-operation QCA ALU, this ALU uses 51% fewer QCA cells and 47% less area

Designing memory cells with a novel approaches based on a new multiplexer in QCA Technology

Transistor-based CMOS technology has many drawbacks such that it cannot continue to follow the scaling of Moore’s law in the near future. These drawbacks lead researchers to think about alternatives. Quantum-dot Cellular Automata (QCA) is a nanotechnology that has unique features in terms of size and power consumption. QCA has the ability to represent binary numbers by electrons configuration. The memory circuit is a very important part of the digital system. In QCA technology, there are many approaches presented to accomplish memory cells in both RAM and CAM types. CAM is a type of memory used in high-speed applications. In this thesis, novel approaches to design memory cells are proposed. The proposed approaches are based on a 2:1 multiplexer. Using the proposed approach of RAM cell, a singular form of RAM cell (SFRAMC) is accomplished. In QCA technology, researchers strive to design electronic circuits with an emphasis on minimizing important metrics such as cell count, area, delay, cost and power consumption. The SFRAMC demonstrated significant improvements, with a reduction cell count, occupied area and power consumption by 25%, 24% and 36%. In terms of implementation cost, the SFRAMC saves 43% of the cost when compared to the previous best design. On the other hand, by using the proposed approach of CAM cell, two different structures of the QCA-CAM cell have been introduced. The first proposed CAM cell (FPCAMC) gives improvements in terms of cell count, and delay by 15% and 17% respectively. The second proposed CAM cell (SPCAMC) gives improvements in terms of cell count, and delay by 6% and 17% respectively. In terms of total power consumption, both FPCAMC and SPCAMC have an improvement of about 53% over the best-reported design. The above features of the proposed memory cells (RAM and CAM) could pave the road for designing energy-efficient and cost-efficient memory circuits in the future

Crosstalk computing: circuit techniques, implementation and potential applications

Title from PDF of title [age viewed January 32, 2022Dissertation advisor: Mostafizur RahmanVitaIncludes bibliographical references (page 117-136)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2020This work presents a radically new computing concept for digital Integrated Circuits (ICs), called Crosstalk Computing. The conventional CMOS scaling trend is facing device scaling limitations and interconnect bottleneck. The other primary concern of miniaturization of ICs is the signal-integrity issue due to Crosstalk, which is the unwanted interference of signals between neighboring metal lines. The Crosstalk is becoming inexorable with advancing technology nodes. Traditional computing circuits always tries to reduce this Crosstalk by applying various circuit and layout techniques. In contrast, this research develops novel circuit techniques that can leverage this detrimental effect and convert it astutely to a useful feature. The Crosstalk is engineered into a logic computation principle by leveraging deterministic signal interference for innovative circuit implementation. This research work presents a comprehensive circuit framework for Crosstalk Computing and derives all the key circuit elements that can enable this computing model. Along with regular digital logic circuits, it also presents a novel Polymorphic circuit approach unique to Crosstalk Computing. In Polymorphic circuits, the functionality of a circuit can be altered using a control variable. Owing to the multi-functional embodiment in polymorphic-circuits, they find many useful applications such as reconfigurable system design, resource sharing, hardware security, and fault-tolerant circuit design, etc. This dissertation shows a comprehensive list of polymorphic logic gate implementations, which were not reported previously in any other work. It also performs a comparison study between Crosstalk polymorphic circuits and existing polymorphic approaches, which are either inefficient due to custom non-linear circuit styles or propose exotic devices. The ability to design a wide range of polymorphic logic circuits (basic and complex logics) compact in design and minimal in transistor count is unique to Crosstalk Computing, which leads to benefits in the circuit density, power, and performance. The circuit simulation and characterization results show a 6x improvement in transistor count, 2x improvement in switching energy, and 1.5x improvement in performance compared to counterpart implementation in CMOS circuit style. Nevertheless, the Crosstalk circuits also face issues while cascading the circuits; this research analyzes all the problems and develops auxiliary circuit techniques to fix the problems. Moreover, it shows a module-level cascaded polymorphic circuit example, which also employs the auxiliary circuit techniques developed. For the very first time, it implements a proof-of-concept prototype Chip for Crosstalk Computing at TSMC 65nm technology and demonstrates experimental evidence for runtime reconfiguration of the polymorphic circuit. The dissertation also explores the application potentials for Crosstalk Computing circuits. Finally, the future work section discusses the Electronic Design Automation (EDA) challenges and proposes an appropriate design flow; besides, it also discusses ideas for the efficient implementation of Crosstalk Computing structures. Thus, further research and development to realize efficient Crosstalk Computing structures can leverage the comprehensive circuit framework developed in this research and offer transformative benefits for the semiconductor industry.Introduction and Motivation -- More Moore and Relevant Beyond CMOS Research Directions -- Crosstalk Computing -- Crosstalk Circuits Based on Perception Model -- Crosstalk Circuit Types -- Cascading Circuit Issues and Sollutions -- Existing Polymorphic Circuit Approaches -- Crosstalk Polymorphic Circuits -- Comparison and Benchmarking of Crosstalk Gates -- Practical Realization of Crosstalk Gates -- Poential Applications -- Conclusion and Future Wor