Imperfection-Aware Design of CNFET Digital VLSI Circuits

Carbon nanotube field-effect transistor (CNFET) is one of the promising candidates as extensions to silicon CMOS devices. The CNFET, which is a 1-D structure with a near-ballistic transport capability, can potentially offer excellent device characteristics and order-of-magnitude better energy-delay product over standard CMOS devices. Significant challenges in CNT synthesis prevent CNFETs today from achieving such ideal benefits. CNT density variation and metallic CNTs are the dominant type of CNT variations/imperfections that cause performance variation, large static power consumption, and yield degradation. We present an imperfection-aware design technique for CNFET digital VLSI circuits by: 1) Analytical models that are developed to analyze and quantify the effects of CNT density variation on device characteristics, gate and system levels delays. The analytical models, which were validated by comparison to real experimental/simulation data, enables us to examine the space of CNFET combinational, sequential and memory cells circuits to minimize delay variations. Using these model, we drive CNFET processing and circuit design guidelines to manage/overcome CNT density variation. 2) Analytical models that are developed to analyze the effects of metallic CNTs on device characteristics, gate and system levels delay and power consumption. Using our presented analytical models, which are again validated by comparison with simulation data, it is shown that the static power dissipation is a more critical issue than the delay and the dynamic power of CNFET circuits in the presence of m-CNTs. 3) CNT density variation and metallic CNTs can result in functional failure of CNFET circuits. The complete and compact model for CNFET probability of failure that consider CNT density variation and m-CNTs is presented. This analytical model is applied to analyze the logical functional failures. The presented model is extended to predict opportunities and limitations of CNFET technology at todays Gigascale integration and beyond.\u2

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Variability and reliability analysis of carbon nanotube technology in the presence of manufacturing imperfections

In 1925, Lilienfeld patented the basic principle of field effect transistor (FET). Thirty-four years later, Kahng and Atalla invented the MOSFET. Since that time, it has become the most widely used type of transistor in Integrated Circuits (ICs) and then the most important device in the electronics industry. Progress in the field for at least the last 40 years has followed an exponential behavior in accordance with Moore¿s Law. That is, in order to achieve higher densities and performance at lower power consumption, MOS devices have been scaled down. But this aggressive scaling down of the physical dimensions of MOSFETs has required the introduction of a wide variety of innovative factors to ensure that they could still be properly manufactured. Transistors have expe- rienced an amazing journey in the last 10 years starting with strained channel CMOS transistors at 90nm, carrying on the introduction of the high-k/metal-gate silicon CMOS transistors at 45nm until the use of the multiple-gate transistor architectures at 22nm and at recently achieved 14nm technology node. But, what technology will be able to produce sub-10nm transistors? Different novel materials and devices are being investigated. As an extension and enhancement to current MOSFETs some promising devices are n-type III-V and p-type Germanium FETs, Nanowire and Tunnel FETs, Graphene FETs and Carbon Nanotube FETs. Also, non-conventional FETs and other charge-based information carrier devices and alternative information processing devices are being studied. This thesis is focused on carbon nanotube technology as a possible option for sub-10nm transistors. In recent years, carbon nanotubes (CNTs) have been attracting considerable attention in the field of nanotechnology. They are considered to be a promising substitute for silicon channel because of their small size, unusual geometry (1D structure), and extraordinary electronic properties, including excellent carrier mobility and quasi-ballistic transport. In the same way, carbon nanotube field-effect transistors (CNFETs) could be potential substitutes for MOSFETs. Ideal CNFETs (meaning all CNTs in the transistor behave as semiconductors, have the same diameter and doping level, and are aligned and well-positioned) are predicted to be 5x faster than silicon CMOS, while consuming the same power. However, nowadays CNFETs are also affected by manufacturing variability, and several significant challenges must be overcome before these benefits can be achieved. Certain CNFET manufacturing imperfections, such as CNT diameter and doping variations, mispositioned and misaligned CNTs, high metal-CNT contact resistance, the presence of metallic CNTs (m-CNTs), and CNT density variations, can affect CNFET performance and reliability and must be addressed. The main objective of this thesis is to analyze the impact of the current CNFET manufacturing challenges on multi-channel CNFET performance from the point of view of variability and reliability and at different levels, device and circuit level. Assuming that CNFETs are not ideal or non-homogeneous because of today CNFET manufacturing imperfections, we propose a methodology of analysis that based on a CNFET ideal compact model is able to simulate heterogeneous or non-ideal CNFETs; that is, transistors with different number of tubes that have different diameters, are not uniformly spaced, have different source/drain doping levels, and, most importantly, are made up not only of semiconducting CNTs but also metallic ones. This method will allow us to analyze how CNT-specific variations affect CNFET device characteristics and parameters and CNFET digital circuit performance. Furthermore, we also derive a CNFET failure model and propose an alternative technique based on fault-tolerant architectures to deal with the presence of m-CNTs, one of the main causes of failure in CNFET circuits

Atténuation des interactions électromagnétiques entre le module de détection LabPET II et l’IRM

Les scanners TEP/IRM simultanés offrent une occassion unique d'examiner en même temps les propriétés anatomiques et fonctionnelles des tissus malins, tout en évitant l'incertitude des systèmes séquentiels de TEP/IRM. Cependant, le couplage électromagnétique entre les deux modalités constitue un défi important à relever. Ces interférences électromagnétiques entravent les performances du scanner et altèrent la qualité d'image de chaque modalité. Bien que les métaux possèdent d'excellentes propriétés de blindage contre les fréquences radioélectriques, ils ne constituent pas nécessairement une option de blindage appropriée pour modifier les champs magnétiques induisant des courants de Foucault dans les couches métalliques. En conséquence, il existe une demande considérable pour un nouveau matériau de protection et une approche originale pour retirer les pièces métalliques du champ de vision IRM. L’objectif de ce projet était d’initier les études en vue de la réalisation d’un scanner TEP/IRM simultané basé sur des modules de détection LabPET II hautement pixélisés afin d’obtenir une résolution spatiale millimétrique pour le cerveau humain et le chien. L'électronique LabPET II comprend des circuits intégrés à application spécifique dans lesquels le signal est numérisé à proximité de la photodiode à avalanche et offre un environnement moins sensible aux interférences électromagnétiques. Pour atteindre l'objectif principal, premièrement, l'effet du matériau métallique des modules de détection LabPET II sur les performances de la TEP et de l'IRM est examiné théoriquement. Les résultats confirment que les composants métalliques du module de détection LabPET II altèrent le champ magnétique, génèrent des courants de Foucault ce qui augmente leur température. Ensuite, les performances électroniques des modules de détection LabPET II sous l’influence de bobines d’IRM faites sur mesure sont examinées. La résolution en énergie et la résolution temporelle se détériorent en présence de bobines RF et de bobines à gradient en raison des perturbations électromagnétiques. Subséquemment, un module de détection LabPET II blindé par une fine couche de composite cuivre-argent est étudié, prouvant que le blindage contre les interférences électromagnétiques avec le composite rétablit les performances en TEP, fournissant moins d'induction par courants de Foucault. En outre, une nouvelle configuration de blindage basée sur un composite de couche flexible de nanotubes de carbone a été fabriquée pour limiter les interférences électromagnétiques. Les composites de nanotubes de carbone créent une couche hautement conductrice avec des chemins conducteurs minimaux, ce qui permet de réduire les courants de Foucault. Le principal résultat scientifique de ce projet est que le blindage composite empêche les interférences de basses et hautes fréquences et réduit l'induction de courants de Foucault, offrant ainsi la flexibilité nécessaire pour acquérir une séquence rapide de commutation de gradients. D'un point de vue technique, le module de détection LabPET II ainsi blindé présente une excellente performance dans un environnement de type IRM, ce qui permet de concevoir un insert TEP basé sur la technologie LabPET II.Abstract: Simultaneous PET/ MRI scanners provide a unique opportunity to investigate anatomical and functional properties of malignant tissues at the same time while avoiding the uncertainty of a sequential PET/MRI systems. However, electromagnetic coupling between the two modalities is a significant challenge that needs to be addressed. These electromagnetic interferences (EMI) hinder the performance of both scanners and distort the image quality of each modality. Although metals have excellent radio-frequency shielding properties, they are not necessarily an appropriate shielding option for altering magnetic fields that induce eddy currents in any metallic layer. Thus, there is a considerable demand for a new shielding material and an original approach to remove metallic parts from the MRI field of view. The objective of this project was to initiate the realization of a simultaneous PET/MRI scanner based on highly pixelated LabPET II detection modules to achieve millimeter spatial resolution for the human brain and dogs. The LabPET II electronics include application specific integrated circuits where the signal is digitized near the avalanche photodiode and offers an environment less susceptible to EMI. To fulfill the main aim, for the first time, the effect of the metallic material of LabPET II on PET and MRI performance was theoretically examined. Results confirm that metallic components of the LabPET II detection modules distort the magnetic field, generate eddy currents, and increase temperature. Then, the LabPET II electronics performance under the influence of custom-made MRI coils was investigated. Its energy and timing resolutions deteriorate in the presence of both RF and gradient signals because of EMIs. Thus, a LabPET II detection module shielded by a thin layer of the copper-silver composite was investigated, proving that shielding EMIs with the composite restores the PET performance, with less eddy current induction. Besides, a new shielding configuration based on a flexible layer of carbon nanotube (CNT) composite was fabricated to limit the EMIs. The CNT composite creates a highly conductive layer with minimal conductive paths that allows eddy currents to be decreased. The primary scientific outcome of this project is that the novel composite shielding rejects both low and high-frequency interferences and reduces eddy current induction, offering the flexibility to acquire a fast gradient switching sequence. From a technical point of view, the shielded LabPET II detection module demonstrates an excellent performance in an MRI-like environment supporting the feasibility of designing a PET-insert based on LabPET II technology

Appropriateness of Imperfect CNFET Based Circuits for Error Resilient Computing Systems

With superior device performance consistently reported in extremely scaled dimensions, low dimensional materials (LDMs), including Carbon Nanotube Field Effect Transistor (CNFET) based technology, have shown the potential to outperform silicon for future transistors in advanced technology nodes. Studies have also demonstrated orders of magnitude improvement in energy efficiency possible with LDMs, in comparison to silicon at competing technology nodes. However, the current fabrication processes for these materials suffer from process imperfections and still appear to be inadequate to compete with silicon for the mainstream high volume manufacturing. Among the LDMs, CNFETs are the most widely studied and closest to high volume manufacturing. Recent works have shown a significant increase in the complexity of CNFET based systems, including demonstration of a 16-bit microprocessor. However, the design of such systems has involved significantly wider-than-usual transistors and avoidance of certain logic combinations. The resulting complexity of several thousand transistors in such systems is still far from the requirements of high-performance general-purpose computing systems having billions of transistors. With the current progress of the process to fabricate CNFETs, their introduction in mainstream manufacturing is expected to take several more years. For an earlier technology adoption, CNFETs appear to be suited for error-resilient computing systems where errors during computation can be tolerated to a certain degree. Such systems relax the need for precise circuits and a perfect process while leveraging the potential energy benefits of CNFET technology in comparison to conventional Si technology. In this thesis, we explore the potential applications using an imperfect CNFET process for error-resilient computing systems, including the impact of the process imperfections at the system level and methods to improve it. The current most widely adopted fabrication process for CNFETs (separation and placement of solution-based CNTs) still suffers from process imperfections, mainly from open CNTs due to missing of CNTs (in trenches connecting source and drain of CNFET). A fair evaluation of the performance of CNFET based circuits should thus take into consideration the effect of open CNTs, resulting in reduced drive currents. At the circuit level, this leads to failures in meeting 1) the minimum frequency requirement (due to an increase in critical path delay), and 2) the noise suppression requirement. We present a methodology to accurately capture the effect of open CNT imperfection in the state-of-the-art CNFET model, for circuit-level performance evaluation (both delay and glitch vulnerability) of CNFET based circuits using SPICE. A Monte Carlo simulation framework is also provided to investigate the statistical effect of open CNT imperfection on circuit-level performance. We introduce essential metrics to evaluate glitch vulnerability and also provide an effective link between glitch vulnerability and circuit topology. The past few years have observed significant growth of interest in approximate computing for a wide range of applications, including signal processing, data mining, machine learning, image, video processing, etc. In such applications, the result quality is not compromised appreciably, even in the presence of few errors during computation. The ability to tolerate few errors during computation relaxes the need to have precise circuits. Thus the approximate circuits can be designed, with lesser nodes, reduced stages, and reduced capacitance at few nodes. Consequently, the approximate circuits could reduce critical path delays and enhanced noise suppression in comparison to precise circuits. We present a systematic methodology utilizing Reduced Ordered Binary Decision Diagrams (ROBDD) for generating approximate circuits by taking an example of 16-bit parallel prefix CNFET adder. The approximate adder generated using the proposed algorithm has ~ 5x reduction in the average number of nodes failing glitch criteria (along paths to primary output) and 43.4% lesser Energy Delay Product (EDP) even at high open CNT imperfection, in comparison to the ideal case of no open CNT imperfection, at a mean relative error of 3.3%. The recent boom of deep learning has been made possible by VLSI technology advancement resulting in hardware systems, which can support deep learning algorithms. These hardware systems intend to satisfy the high-energy efficiency requirement of such algorithms. The hardware supporting such algorithms adopts neuromorphic-computing architectures with significantly less energy compared to traditional Von Neumann architectures. Deep Neural Networks (DNNs) belonging to deep learning domain find its use in a wide range of applications such as image classification, speech recognition, etc. Recent hardware systems have demonstrated the implementation of complex neural networks at significantly less power. However, the complexity of applications and depths of DNNs are expected to drastically increase in the future, imposing a demanding requirement in terms of scalability and energy efficiency of hardware technology. CNFET technology can be an excellent alternative to meet the aggressive energy efficiency requirement for future DNNs. However, degradation in circuit-level performance due to open CNT imperfection can result in timing failure, thus distorting the shape of non-linear activation function, leading to a significant degradation in classification accuracy. We present a framework to obtain sigmoid activation function considering the effect of open CNT imperfection. A digital neuron is explored to generate the sigmoid activation function, which deviates from the ideal case under imperfect process and reduced time period (increased clock frequency). The inherent error resilience of DNNs, on the other hand, can be utilized to mitigate the impact of imperfect process and maintain the shape of the activation function. We use pruning of synaptic weights, which, combined with the proposed approximate neuron, significantly reduces the chance of timing failures and helps to maintain the activation function shape even at high process imperfection and higher clock frequencies. We also provide a framework to obtain classification accuracy of Deep Belief Networks (class of DNNs based on unsupervised learning) using the activation functions obtained from SPICE simulations. By using both approximate neurons and pruning of synaptic weights, we achieve excellent system accuracy (only < 0.5% accuracy drop) with 25% improvement in speed, significant EDP advantage (56.7% less) even at high process imperfection, in comparison to a base configuration of the precise neuron and no pruning with the ideal process, at no area penalty. In conclusion, this thesis provides directions for the potential applicability of CNFET based technology for error-resilient computing systems. For this purpose, we present methodologies, which provide approaches to assess and design CNFET based circuits, considering process imperfections. We accomplish a DBN framework for digit recognition, considering activation functions from SPICE simulations incorporating process imperfections. We demonstrate the effectiveness of using approximate neuron and synaptic weight pruning to mitigate the impact of high process imperfection on system accuracy

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Preparation and characterization of Carbon Nanotube based vertical interconnections for integrated circuits: Preparation and characterization of Carbon Nanotube based verticalinterconnections for integrated circuits

(ULSI) causes an increase of the resistance of the wiring system by increased scattering of electrons at side walls and grain boundaries in the state of the art Cu technology, which increases the RC delay of the interconnect system and thus degrades the performance of the device. The outstanding properties of carbon nanotubes (CNT) such as a large mean free path, a high thermal conductance and a large resistance against electromigration make them an ideal candidate to replace Cu in future feature nodes. The present thesis contributes to the preparation and properties of CNT based vertical interconnections (vias). In addition, all processes applied during the fabrication are compatible to ULSI and an interface between CNT based vias and a Cu metallization is studied. The methodology for the evaluation of CNT based vias is improved; it is highlighted that by measuring the resistance of one multiwall CNT and taking into account the CNT density, the performance of the CNT based vias can be predicted accurately. This provides the means for a systematic evaluation of different integration procedures and materials. The lowest contact resistance is obtained for carbide forming metals, as long as oxidation during the integration is avoided. Even though metal-nitrides exhibit an enhanced contact resistance, they are recommended to be used at the bottom metallization in order to minimize the oxidation of the metal-CNT contact during subsequent processing steps. Overall a ranking for the materials from the lowest to the highest contact resistance is obtained: Ta < Ti < TaN < TiN « TiO2 « Ta2O5 Furthermore the impact of post CNT growth procedures as chemical mechanical planarization, HF treatment and annealing procedures after the CNT based via fabrication are evaluated. The conductance of the incorporated CNTs and the applicable electrical transport regime relative to the CNT quality and the CNT length is discussed. In addition, a strong correlation between the temperature coefficient of resistance and the initial resistance of the CNT based vias at room temperature has been observed.Die kontinuierliche Miniaturisierung der charakteristischen Abmessungen in hochintegrierten Schaltungen (ULSI) verursacht einen Anstieg des Widerstandes im Zuleitungssystem aufgrund der erhöhten Streuung von Elektronen an Seitenwänden und Korngrenzen in der Cu-Technologie, wodurch die Verzögerungszeit des Zuleitungssystems ansteigt. Die herausragenden Eigenschaften von Kohlenstoffnanoröhren (CNT), wie eine große mittlere freie Weglänge, hohe thermische Leitfähigkeit und eine starke Resistenz gegenüber Elektromigration machen diese zu einem idealen Kandidaten, um Cu in zukünftigen Technologiegenerationen zu ersetzen. Die vorliegende Arbeit beschreibt die Herstellung und daraus resultierenden Eigenschaften von Zwischenebenenkontakten (Vias) basierend auf CNTs. Alle verwendeten Prozessierungsschritte sind kompatibel mit der Herstellung von hochintegrierten Schaltkreisen und eine Schnittstelle zwischen den CNT Vias und einer Cu-Metallisierung ist vorhanden. Insbesondere das Verfahren zur Evaluierung von CNT Vias wurde durch den Einsatz verschiedener Methoden verbessert. Insbesondere soll hervorgehoben werden, dass durch die Messung des Widerstandes eines einzelnen CNTs, bei bekannter CNT Dichte, der Via Widerstand sehr genau vorausgesagt werden kann. Dies ermöglicht eine systematische Untersuchung des Einflusses der verschiedenen Prozessschritte und der darin verwendeten Materialien auf den Via Widerstand. Der niedrigste Kontaktwiderstand wird für Karbidformierende Metalle erreicht, solange Oxidationsprozesse ausgeschlossen werden können. Obwohl Metallnitride einen höheren Kontaktwiderstand aufweisen, sind diese für die Unterseitenmetallisierung zu empfehlen, da dadurch die Oxidation der leitfähigen Schicht minimiert wird. Insgesamt kann eine Reihenfolge beginnend mit dem niedrigsten zum höchsten Kontaktwiderstand aufgestellt werden: Ta < Ti < TaN < TiN « TiO2 « Ta2O5 Desweiteren wurde der Einfluss von Verfahren nach dem CNTWachstum wie die chemischmechanische Planarisierung, eine HF Behandlung und einer Temperaturbehandlung evaluiert, sowie deren Einfluss auf die elektrischen Parameter des Vias untersucht. Die Leitfähigkeit der integrierten CNTs und die daraus resultierenden elektrischen Transporteigenschaften in Abhängigkeit der CNT Qualität und Länge werden besprochen. Ebenso wird die starke Korrelation zwischen dem Temperaturkoeffizienten des elektrischen Widerstandes und des Ausgangswiderstandes der CNT basierten Vias bei Raumtemperatur diskutiert

Electrosharpening of Tungsten Probes for Arc Discharge Assembly of Carbon Nanotubes

Ultra-sharp tungsten probes fill a key role in science for allowing measurements and interactions at the nanoscale. However, their current method of fabrication is outdated, fundamentally limited in length, sharpness and consistency, and often referred to as an ‘art’. A new process of fabricating ultra-sharp tungsten probes known as ‘Tungstate Sharpening’ was invented. This electrochemical process utilises solely the WO42- by-product to create a gradient of etching which results in a sharpening effect. It was shown to electrochemically etch probes controllably over lengths from 0.5 – 4.5 mm with tip radii of 10 nm via a fully automated process. Tungstate sharpening overcomes many of the limitations of the previous methods as well as creating new opportunities for further research into electrosharpening. Tungstate sharpening was improved to use bulk coulometry analysis which allows users to select specific probe lengths. The process was also modified to allow etching of five probes simultaneously, which is fundamentally impossible with conventional techniques. Furthermore, this batch process was improved with the application of a magnetic field that reduced fabrication time and inconsistencies. Flow simulations were conducted to confirm experimental observations of the electrode separation influence on turbulence within the electrochemical system, supporting the underlying theory and observations of the tungstate layer. Finally, this processing technique was expanded with various materials and shapes to demonstrate versatility. Razor blades with edge radii of 40 nm were produced demonstrating that electrosharpening is no longer limited to ‘1D’ objects. Another process was developed to fabricate carbon nanotubes (CNTs) as a macroscopic material. ‘Arc Assembly’ was invented to explore the possibility of forming long chains of CNTs whilst maintaining the sp2 crystalline bonding within and between individual CNTs. For the first time, dielectrophoresis was combined with arc discharges to form ‘threads’ of CNTs using the tungsten probes produced. The tungsten probes were applied as electrodes for dielectrophoresis of CNT chains and simultaneous arcing between them. Multiple high voltage circuits with outputs ranging from beneath the breakdown threshold and negative K(ω) up to 1000 V and 8 MHz were constructed and tested. Dispersed carbon nanotube mixtures for a variety of dielectric organic fluids, solvents and polymers were placed between the electrodes. The resulting phenomenon was the assembly of dielectrophoretic chains with arc-induced adhesion between nanotubes: termed as “Arc Assembly”. As Arc Assembly was developed, the CNT threads were analysed using scanning electron microscopy, energy dispersive X-ray spectroscopy, transmission electron microscopy and Raman analysis. Observations were made of both amorphous and crystalline links between the CNTs, as well as embedded CNT chains within in-situ formed polymer composites. The process produced threads of carbon nanotubes up to 5 mm length, indicating that this may be a viable means of exploiting CNTs in every-day life

Electromechanical Switches Fabricated by Electrophoretic Deposition of Single Wall Carbon Nanotube Films

University of Minnesota Ph.D. dissertation.August 2015. Major: Electrical/Computer Engineering. Advisor: Stephen Campbell. 1 computer file (PDF); xi, 110 pages.Power dissipation is a critical problem of CMOS devices especially for mobile applications. Many efforts have been made to solve the problem, but there are still major issues associated with scaling the device size. Micro electromechanical (MEMS) and nano electromechanical (NEMS) devices are one candidate to solve the problems because of their excellent standby leakage. However, the switches have a tradeoff between low operating power and high device speed. Suspended beams with low mass density and good mechanical properties provide a way to optimize the device. Carbon nanotubes (CNTs) have the low mass density and excellent mechanical properties to enable high performance MEMS/NEMS devices. However, the high temperature required for the direct synthesis for CNTs makes it difficult for them to be compatible with a substrate containing transistors. Therefore, continuous film deposition techniques are investigated with low temperature (< 300 C). Electrophoretic deposition (EPD) is a simple and versatile processing method to deposit carbon nanotubes on the substrate at room temperature. The movement of the charged CNTs in suspension occurs by an applied electric field. The deposited CNT film thickness can be controlled through the applied voltage and process time. We demonstrate the use of an EPD process to deposit various thicknesses of CNT films. Film thicknesses are studied as a function of, deposition time, electric field strength, and suspension concentration. The deposition mechanism of the EPD process for carbon nanotube layers was explained with experimental data. We determined the film mass density and electrical/optical properties of SWCNT films. Rutherford backscattering spectroscopy was used to determine the film mass density. Films created in this manner had a mass density that varies with thickness from 0.12 to 0.54 g/cm3 and a resistivity of 2.1410-3 Ω∙cm. For the mechanical property measurements, we describe a technique to fabricate free-standing thin films using modified Langmuir-Blodgett method. Then we extracted the Young’s modulus of the film from the load-displacement data from nanoindentation using the appropriate modeling. The Young’s modulus had a range of 4.72 to 5.67 GPa, independent of deposited thickness. We fabricated two-terminal fixed beam switches with SWCNT thin films using the EPD process. Device pull-in voltages under 1V were achieved by decreasing the air-gap. The pull-in voltages were compared with the calculated results using the device geometry and extracted Young’s modulus from nanoindentation. Generally good agreement was observed. Also, we found a range of 2.4 to 3.5 MHz resonant frequency. However, we encountered several problems with the device including a gradual turn-on, hysteresis between pull-in and pull-out voltage, changes in the pull-in voltages with repeated on-off cycling, and early failure due to moisture absorption during testing in the air. Mechanisms for these observations are postulated. Further work is needed to improve device performance and reliability

Cutting Edge Nanotechnology

The main purpose of this book is to describe important issues in various types of devices ranging from conventional transistors (opening chapters of the book) to molecular electronic devices whose fabrication and operation is discussed in the last few chapters of the book. As such, this book can serve as a guide for identifications of important areas of research in micro, nano and molecular electronics. We deeply acknowledge valuable contributions that each of the authors made in writing these excellent chapters