20 research outputs found
Designing Testability Into An Existing Microprocessor Board
Master of ScienceDepartment of Electrical and Computer EngineeringThis thesis presents the hardware implementation of a microprocessor system built according to the microprocessor-controlled Built-In Self-Test (BIST) techniques as presented by Gordon [Gordon 1991 a]. It covers issues relating to the isolation of the edge connector and secondary board areas, to the use and function of a fieldprogrammable gate array (Logic Cell Array)n", to the implementation of electronic wraparounds, and to the general design of the software to support the testability features. In addition, it covers the general use of the ANSI/IEEE Std. 1149.1 test bus for diagnosis, isolation, and board-level partitioning
Phase Locking Authentication for Scan Architecture
Scan design is a widely used Design for Testability (DfT) approach for digital circuits. It provides a high level of controllability and observability resulting in a high fault coverage. To achieve a high level of testability, scan architecture must provide access to the internal nodes of the circuit-under-test (CUT). This access however leads to vulnerability in the security of the CUT. If an unrestricted access is provided through a scan architecture, unlimited test vectors can be applied to the CUT and its responses can be captured. Such an unrestricted access to the CUT can potentially undermine the security of the critical information stored in the CUT. There is a need to secure scan architecture to prevent hardware attacks however a secure solution may limit the CUT testability. There is a trade-off between security and testability, therefore, a secure scan architecture without hindering its controllability and observability is required. Three solutions to secure scan architecture have been proposed in this thesis. In the first method, the tester is authenticated and the number of authentication attempts has been limited. In the second method, a Phase Locked Loop (PLL) is utilized to secure scan architecture. In the third method, the scan architecture is secured through a clock and data recovery (CDR) technique. This is a manuscript based thesis and the results of this study have been published in two conference proceedings. The latest results have also been prepared as an article for submission to a high rank conference
Design for pre-bond testability in 3D integrated circuits
In this dissertation we propose several DFT techniques specific to 3D
stacked IC systems. The goal has explicitly been to create techniques that
integrate easily with existing IC test systems. Specifically, this means
utilizing scan- and wrapper-based techniques, two foundations
of the digital IC test industry.
First, we describe a general test architecture for 3D ICs. In this
architecture, each tier of a 3D design is wrapped in test control logic that
both manages tier test
pre-bond and integrates the tier into the large test architecture post-bond.
We describe a new kind of boundary scan to provide the necessary test control
and observation of the partial circuits, and we propose
a new design methodology for test hardcore that ensures both pre-bond functionality
and post-bond optimality. We present the application of these techniques to
the 3D-MAPS test vehicle, which has proven their effectiveness.
Second, we extend these DFT techniques to circuit-partitioned designs. We find
that boundary scan design is generally sufficient, but that some 3D designs require
special DFT treatment. Most importantly, we demonstrate that the functional
partitioning inherent in 3D design can potentially decrease the total test cost
of verifying a circuit.
Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithm
co-designs the pre-bond and post-bond wrappers to simultaneously minimize test
time and routing cost. On average, our algorithm utilizes over 90% of the wires
in both the pre-bond and post-bond wrappers.
Finally, we look at the 3D vias themselves to develop a low-cost, high-volume
pre-bond test methodology appropriate for production-level test. We describe
the shorting probes methodology, wherein large test probes are used to contact
multiple small 3D vias. This technique is an all-digital test method that
integrates seamlessly into existing test flows. Our
experimental results demonstrate two key facts: neither the large capacitance
of the probe tips nor the process variation in the 3D vias and the probe tips
significantly hinders the testability of the circuits.
Taken together, this body of work defines a complete test methodology for
testing 3D ICs pre-bond, eliminating one of the key hurdles to the
commercialization of 3D technology.PhDCommittee Chair: Lee, Hsien-Hsin; Committee Member: Bakir, Muhannad; Committee Member: Lim, Sung Kyu; Committee Member: Vuduc, Richard; Committee Member: Yalamanchili, Sudhaka
Design for testability in hardware-software systems
Clearly, in today's complex systems, hardware and software approaches to DFT must work together to achieve a successful overall solution. The authors investigate existing and new concepts that may lead to a single design for test strategy in the futur
New techniques for functional testing of microprocessor based systems
Electronic devices may be affected by failures, for example due to physical defects. These defects may be introduced during the manufacturing process, as well as during the normal operating life of the device due to aging. How to detect all these defects is not a trivial task, especially in complex systems such as processor cores. Nevertheless, safety-critical applications do not tolerate failures, this is the reason why testing such devices is needed so to guarantee a correct behavior at any time. Moreover, testing is a key parameter for assessing the quality of a manufactured product.
Consolidated testing techniques are based on special Design for Testability (DfT) features added in the original design to facilitate test effectiveness. Design, integration, and usage of the available DfT for testing purposes are fully supported by commercial EDA tools, hence approaches based on DfT are the standard solutions adopted by silicon vendors for testing their devices.
Tests exploiting the available DfT such as scan-chains manipulate the internal state of the system, differently to the normal functional mode, passing through unreachable configurations. Alternative solutions that do not violate such functional mode are defined as functional tests.
In microprocessor based systems, functional testing techniques include software-based self-test (SBST), i.e., a piece of software (referred to as test program) which is uploaded in the system available memory and executed, with the purpose of exciting a specific part of the system and observing the effects of possible defects affecting it. SBST has been widely-studies by the research community for years, but its adoption by the industry is quite recent.
My research activities have been mainly focused on the industrial perspective of SBST. The problem of providing an effective development flow and guidelines for integrating SBST in the available operating systems have been tackled and results have been provided on microprocessor based systems for the automotive domain. Remarkably, new algorithms have been also introduced with respect to state-of-the-art approaches, which can be systematically implemented to enrich SBST suites of test programs for modern microprocessor based systems. The proposed development flow and algorithms are being currently employed in real electronic control units for automotive products.
Moreover, a special hardware infrastructure purposely embedded in modern devices for interconnecting the numerous on-board instruments has been interest of my research as well. This solution is known as reconfigurable scan networks (RSNs) and its practical adoption is growing fast as new standards have been created. Test and diagnosis methodologies have been proposed targeting specific RSN features, aimed at checking whether the reconfigurability of such networks has not been corrupted by defects and, in this case, at identifying the defective elements of the network. The contribution of my work in this field has also been included in the first suite of public-domain benchmark networks
Tester for chosen sub-standard of the IEEE 802.1Q
Tato práce se zabĂ˝vá analyzovánĂm IEEE 802.1Q standardu TSN skupiny a návrhem testovacĂho modulu. TestovacĂ modul je napsán v jazyku VHDL a je moĹľnĂ© jej implementovat do Intel Stratix® V GX FPGA (5SGXEA7N2F45C2) vĂ˝vojovĂ© desky. Standard IEEE 802.1Q (TSN) definuje deterministickou komunikace pĹ™es Ethernet sĂt, v reálnĂ©m ÄŤase, poĹľĂvánĂm globálnĂho ÄŤasu a správnĂ˝m rozvrhem vysĂlánĂm a pĹ™Ăjmem zpráv. HlavnĂ funkce tohoto standardu jsou: ÄŤasová synchronizace, plánovánĂ provozu a konfigurace sĂtÄ›. KaĹľdá z tÄ›chto funkcĂ je definovaná pomocĂ vĂce rĹŻznĂ˝ch podskupin tohoto standardu. Podle definice IEEE 802.1Q standardu je moĹľno tyto podskupiny vzájemnÄ› libovolnÄ› kombinovat. NÄ›kterĂ© podskupiny standardu nemohou fungovat nezávisle, musĂ vyuĹľĂvat funkce jinĂ˝ch podskupin standardu. Realizace funkce podskupin standardu je moĹľná softwarovÄ›, hardwarovÄ›, nebo jejich kombinacĂ. Na základÄ› výše uvedenĂ˝ch fakt, implementace podskupin standardu, kterĂ© jsou softwarovÄ› souvisejĂcĂ, byly vylouÄŤenĂ©. Taky byly vylouÄŤenĂ© podskupiny standardĹŻ, kterĂ© jsou závislĂ© na jinĂ˝ch podskupinách. IEEE 802.1Qbu byl vybrán jako vhodná část pro realizaci hardwarovĂ©ho testu. RĹŻznĂ© zpĹŻsoby testovánĂ byly vysvÄ›tleny jako DFT, BIST, ATPG a dalšà jinĂ© techniky. Pro hardwarovĂ© testovánĂ byla vybrána „Protocol Aware (PA)“technika, protoĹľe tato technika zrychluje testovánĂ, dovoluje opakovanou pouĹľitelnost a taky zkracuje dobu uvedenĂ na trh. TestovacĂ modul se skládá ze dvou objektĹŻ (generátor a monitor), kterĂ© majĂ implementovanou IEEE 802.1Qbu podskupinu standardu. Funkce generátoru je vygenerovat náhodnĂ© nebo nenáhodnĂ© impulzy a potom je poslat do testovanĂ©ho zaĹ™Ăzeni ve správnĂ©m definovanĂ©m protokolu. Funkce monitoru je pĹ™ijat ethernet rámce a ověřit jejich správnost. Objekty jsou navrhnuty stejnĂ˝m zpĹŻsobem na „TOP“úrovni a skládajĂ se ze ÄŤtyĹ™ modulĹŻ: Avalon MM rozhranĂ, dvou šablon a jednoho portu. Avalon MM rozhranĂ bylo vytvoĹ™eno pro komunikaci softwaru s hardwarem. Tento modul pĹ™ijme pakety ze softwaru a potom je dekĂłduje podle definovanĂ©ho protokolu a „pod-protokolu “. „Pod-protokol“se skládá z pĹ™Ăkazu a hodnoty danĂ©ho pĹ™Ăkazu. Podle dekĂłdovanĂ©ho pĹ™Ăkazu a hodnot danĂ˝ch pĹ™Ăkazem je kontrolovanĂ˝ celĂ˝ objekt. Ĺ ablona se pouĹľĂvá na generovánĂ nebo ověřovánĂ náhodnĂ˝ch nebo nenáhodnĂ˝ch dat. DvÄ› šablony byly implementovány pro expresnĂ ověřovánĂ nebo preempÄŤnĂ transakce, definovanĂ© IEEE 802.1Qbu. Porty byly vytvoĹ™enĂ© pro komunikaci mezi testovanĂ˝m zaĹ™ĂzenĂm a šablonou podle danĂ©ho standardu. Port „generátor“má za Ăşkol vybrat a vyslat rámce podle priority a ÄŤasu vysĂlanĂ. Port „monitor“pĹ™ijme rámce do „content-addressable memory”, která ověřuje priority rámce a podle toho je posĂlá do správnĂ© šablony. VĂ˝sledky prokázaly, Ĺľe tato testovacĂ technika dosahuje vysokĂ© rychlosti a rychlĂ© implementace.This master paper is dealing with the analysis of IEEE 802.1Q group of TSN standards and with the design of HW tester. Standard IEEE 802.1Qbu has appeared to be an optimal solution for this paper. Detail explanation of this sub-standard are included in this paper. As HW test the implementation, a protocol aware technique was chosen in order to accelerate testing. Paper further describes architecture of this tester, with detail explanation of the modules. Essential issue of protocol aware controlling objects by SW, have been resolved and described. Result proof that this technique has reached higher speed of testing, reusability, and fast implementation.
High-speed, economical design implementation of transit network router
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.Includes bibliographical references (p. 88-90).by Kazuhiro Hara.M.S