Design Techniques for High-Performance SAR A/D Converters

The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs. ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption. Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s. The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology

New technologies for radiation-hardening analog to digital converters

Surveys of available Analog to Digital Converters (ADC) suitable for precision applications showed that none have the proper combination of accuracy and radiation hardness to meet space and/or strategic weapon requirements. A development program which will result in an ADC device which will serve a number of space and strategic applications. Emphasis was placed on approaches that could be integrated onto a single chip within three to five years

Six Degree of Freedom Force/Torque Sensor

The use of robots and manipulators in many kind of applications, such as scientific, medical or industrial ones, requires efficient multi-component force sensing schemes to control the force exerted by the robot end-effector on a human or an object. A multiaxis force sensor can be used to measure the contact force as accurately as possible, and to feed it back to the command signal so that the robot can achieve the pre-specified contact force. As the commercial force sensors are complex and expensive, the goal of this work is to make a multiaxis force sensor that could rThis work describes the design, development and calibration of a complete six?degree-of-freedom force and torque sensor. Compared to commercial sensors, this design has the advantage of simplicity and low cost. The sensor was machined from aluminium, and sensed by an array of commercial low-cost strain gauges. As a sensor, it could be applied in multi-DOF industrial, scientific and medical robotic systems, for instance

DESIGN OF LOW-POWER LOW-VOLTAGE SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS

Ph.DDOCTOR OF PHILOSOPH

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Department of Electrical EngineeringA Sensor system is advanced along sensor technologies are developed. The performance improvement of sensor system can be expected by using the internet of things (IoT) communication technology and artificial neural network (ANN) for data processing and computation. Sensors or systems exchanged the data through this wireless connectivity, and various systems and applications are possible to implement by utilizing the advanced technologies. And the collected data is computed using by the ANN and the efficiency of system can be also improved. Gas monitoring system is widely need from the daily life to hazardous workplace. Harmful gas can cause a respiratory disease and some gas include cancer-causing component. Even though it may cause dangerous situation due to explosion. There are various kinds of hazardous gas and its characteristics that effect on human body are different each gas. The optimal design of gas monitoring system is necessary due to each gas has different criteria such as the permissible concentration and exposure time. Therefore, in this thesis, conventional sensor system configuration, operation, and limitation are described and gas monitoring system with wireless connectivity and neural network is proposed to improve the overall efficiency. As I already mentioned above, dangerous concentration and permissible exposure time are different depending on gas types. During the gas monitoring, gas concentration is lower than a permissible level in most of case. Thus, the gas monitoring is enough with low resolution for saving the power consumption in this situation. When detecting the gas, the high-resolution is required for the accurate concentration detecting. If the gas type is varied in the above situation, the amount of calculation increases exponentially. Therefore, in the conventional systems, target specifications are decided by the highest requirement in the whole situation, and it occurs increasing the cost and complexity of readout integrated circuit (ROIC) and system. In order to optimize the specification, the ANN and adaptive ROIC are utilized to compute the complex situation and huge data processing. Thus, gas monitoring system with learning-based algorithm is proposed to improve its efficiency. In order to optimize the operation depending on situation, dual-mode ROIC that monitoring mode and precision mode is implemented. If the present gas concentration is decided to safe, monitoring mode is operated with minimal detecting accuracy for saving the power consumption. The precision mode is switched when the high-resolution or hazardous situation are detected. The additional calibration circuits are necessary for the high-resolution implementation, and it has more power consumption and design complexity. A high-resolution Analog-to-digital converter (ADC) is kind of challenges to design with efficiency way. Therefore, in order to reduce the effective resolution of ADC and power consumption, zooming correlated double sampling (CDS) circuit and prediction successive approximation register (SAR) ADC are proposed for performance optimization into precision mode. A Microelectromechanical systems (MEMS) based gas sensor has high-integration and high sensitivity, but the calibration is needed to improve its low selectivity. Conventionally, principle component analysis (PCA) is used to classify the gas types, but this method has lower accuracy in some case and hard to verify in real-time. Alternatively, ANN is powerful algorithm to accurate sensing through collecting the data and training procedure and it can be verified the gas type and concentration in real-time. ROIC was fabricated in complementary metal-oxide-semiconductor (CMOS) 180-nm process and then the efficiency of the system with adaptive ROIC and ANN algorithm was experimentally verified into gas monitoring system prototype. Also, Bluetooth supports wireless connectivity to PC and mobile and pattern recognition and prediction code for SAR ADC is performed in MATLAB. Real-time gas information is monitored by Android-based application in smartphone. The dual-mode operation, optimization of performance and prediction code are adjusted with microcontroller unit (MCU). Monitoring mode is improved by x2.6 of figure-of-merits (FoM) that compared with previous resistive interface.clos

Concepts for smart AD and DA converters

This thesis studies the `smart' concept for application to analog-to-digital and digital-to-analog converters. The smart concept aims at improving performance - in a wide sense - of AD/DA converters by adding on-chip intelligence to extract imperfections and to correct for them. As the smart concept can correct for certain imperfections, it can also enable the use of more efficient architectures, thus yielding an additional performance boost. Chapter 2 studies trends and expectations in converter design with respect to applications, circuit design and technology evolution. Problems and opportunities are identfied, and an overview of performance criteria is given. Chapter 3 introduces the smart concept that takes advantage of the expected opportunities (described in chapter 2) in order to solve the anticipated problems. Chapter 4 applies the smart concept to digital-to-analog converters. In the discussed example, the concept is applied to reduce the area of the analog core of a current-steering DAC. It is shown that a sub-binary variable-radix approach reduces the area of the current-source elements substantially (10x compared to state-of-the-art), while maintaining accuracy by a self-measurement and digital pre-correction scheme. Chapter 5 describes the chip implementation of the sub-binary variable-radix DAC and discusses the experimental results. The results confirm that the sub-binary variable-radix design can achieve the smallest published current-source-array area for the given accuracy (12bit). Chapter 6 applies the smart concept to analog-to-digital converters, with as main goal the improvement of the overall performance in terms of a widely used figure-of-merit. Open-loop circuitry and time interleaving are shown to be key to achieve high-speed low-power solutions. It is suggested to apply a smart approach to reduce the effect of the imperfections, unintentionally caused by these key factors. On high-level, a global picture of the smart solution is proposed that can solve the problems while still maintaining power-efficiency. Chapter 7 deals with the design of a 500MSps open-loop track-and-hold circuit. This circuit is used as a test case to demonstrate the proposed smart approaches. Experimental results are presented and compared against prior art. Though there are several limitations in the design and the measurement setup, the measured performance is comparable to existing state-of-the-art. Chapter 8 introduces the first calibration method that counteracts the accuracy issues of the open-loop track-and-hold. A description of the method is given, and the implementation of the detection algorithm and correction circuitry is discussed. The chapter concludes with experimental measurement results. Chapter 9 introduces the second calibration method that targets the accuracy issues of time-interleaved circuits, in this case a 2-channel version of the implemented track-and-hold. The detection method, processing algorithm and correction circuitry are analyzed and their implementation is explained. Experimental results verify the usefulness of the method

Epälineaarinen vääristymä laajakaistaisissa analogia-digitaalimuuntimissa

This thesis discusses nonlinearities of analog-to-digital converters (ADCs) and their mitigation using digital signal processing (DSP). Particularly wideband radio receivers are considered here including, e.g., the emerging cognitive radio applications. In this kind of receivers, a single ADC converts a mixture of signals at different frequency bands to digital domain simultaneously. Different signals may have considerably different power levels and hence the overall dynamic range can be very large (even 50–60 dB). Therefore, even the smallest ADC nonlinearities can produce considerable amount of nonlinear distortion, which may cause a strong signal to block significantly weaker signal bands. One concrete source of nonlinear distortion is waveform clipping due to improper signal conditioning in the input of an ADC. In the thesis, a mathematical model for this phenomenon is derived through Fourier analysis and is then used as a basis for an adaptive interference cancellation (AIC) method. This is a general method for reducing nonlinear distortion and besides clipping it can be used, e.g., to compensate integral nonlinearity (INL) originating from unintentional deviations of the quantization levels. Additionally, an interpolation method is proposed in this thesis to restore clipped waveforms and hence reduce nonlinear distortion. Through several computer simulations and corresponding laboratory radio signal measurements, the performance of the proposed post-processing methods is illustrated. It can be seen from the results that the methods are able to reduce nonlinear distortion from a weak signal band in a considerable manner when there are strong blocking signals in the neighboring channels. According to the results, the AIC method would be a highly recommendable post-processing technique for modern radio receivers due to its general ability to reduce nonlinear distortion regardless of its source. /Kir10Tässä työssä käsitellään analogia-digitaalimuuntimien (AD-muuntimien) epälineaarisuuksia ja niiden lieventämistä digitaalisen signaalinkäsittelyn (DSP) avulla. Tätä on tarkasteltu erityisesti laajakaistaisten radiovastaanottimien näkökulmasta, joka käsittää mm. tulevat kognitiiviseen radioon liittyvät sovellukset. Tällaisissa vastaanottimissa yksittäinen AD-muunnin muuntaa samanaikaisesti useita eri taajuuskaistoilla olevia signaaleita digitaaliseen muotoon, jolloin yhteenlaskettu dynaaminen alue voi olla hyvin suuri (jopa 50–60 dB). Tämän takia AD-muuntimen pienimmätkin epälineaarisuudet voivat aiheuttaa huomattavasti epälineaarista vääristymää, minkä vuoksi voimakas signaali saattaa häiriöllään peittää muilla taajuuskaistoilla olevia selkeästi heikompia signaaleja. Eräs konkreettinen epälineaarisen vääristymän aiheuttaja on aaltomuodon leikkaantuminen AD-muuntimen sisäänmenossa jännitealueen ylittymisen vuoksi. Tässä työssä johdetaan matemaattinen malli kyseiselle ilmiölle Fourier-analyysin avulla ja käytetään sitä lähtökohtana adaptiiviselle häiriönpoistomenetelmälle (AIC-menetelmä). Se on yleisluonteinen menetelmä epälineaarisen vääristymän vähentämiseksi, ja leikkaantumisen lisäksi sitä voidaan käyttää esimerkiksi kompensoimaan integraalista epälineaarisuutta (INL), joka on peräisin kvantisointitasojen tahattomista poikkeamista. Lisäksi tässä työssä esitellään interpolointimenetelmä leikkaantuneen aaltomuodon ehostamiseen siten, että epälineaarinen häiriö vähenee. Esiteltyjen jälkikäsittelymenetelmien suorituskykyä analysoidaan ja havainnollistetaan useilla tietokonesimulaatiolla sekä niitä vastaavilla radiosignaalien laboratoriomittauksilla. Tuloksista voidaan nähdä, että nämä menetelmät kykenevät poistamaan huomattavasti epälineaarista vääristymää heikolta signaalikaistalta silloin, kun naapurikaistoilla on voimakkaita häiriösignaaleja. Tulosten perusteella AIC-menetelmä olisi erittäin suositeltava jälkikäsittelytekniikka moderneihin radiovastaanottimiin, koska se pystyy yleisesti vähentämään epälineaarista vääristymää riippumatta häiriön alkuperästä

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Analog and Mixed Signal Design towards a Miniaturized Sleep Apnea Monitoring Device

Sleep apnea is a sleep-induced breathing disorder with symptoms of momentary and often repetitive cessations in breathing rhythm or sustained reductions in breathing amplitude. The phenomenon is known to occur with varying degrees of severity in literally millions of people around the world and cause a range of chronicle health issues. In spite of its high prevalence and serious consequences, nearly 80% of people with sleep apnea condition remain undiagnosed. The current standard diagnosis technique, termed polysomnography or PSG, requires the patient to schedule and undergo a complex full-night sleep study in a specially-equipped sleep lab. Due to both high cost and substantial inconvenience, millions of apnea patients are still undiagnosed and thus untreated. This research work aims at a simple, reliable, and miniaturized solution for in-home sleep apnea diagnosis purposes. The proposed solution bears high-level integration and minimal interference with sleeping patients, allowing them to monitor their apnea conditions at the comfort of their homes. Based on a MEMS sensor and an effective apnea detection algorithm, a low-cost single-channel apnea screening solution is proposed. A custom designed IC chip implements the apnea detection algorithm using time-domain signal processing techniques. The chip performs autonomous apnea detection and scoring based on the patient’s airflow signals detected by the MEMS sensor. Variable sensitivity is enabled to accommodate different breathing signal amplitudes. The IC chip was fabricated in standard 0.5-μm CMOS technology. A prototype device was designed and assembled including a MEMS sensor, the apnea detection IC chip, a PSoC platform, and wireless transceiver for data transmission. The prototype device demonstrates a valuable screening solution with great potential to reach the broader public with undiagnosed apnea conditions. In a battery-operated miniaturized medical device, an energy-efficient analog-to-digital converter is an integral part linking the analog world of biomedical signals and the digital domain with powerful signal processing capabilities. This dissertation includes the detailed design of a successive approximation register (SAR) ADC for ultra-low power applications. The ADC adopts an asynchronous 2b/step scheme that halves both conversion time and DAC/digital circuit’s switching activities to reduce static and dynamic energy consumption. A low-power sleep mode is engaged at the end of all conversion steps during each clock period. The technical contributions of this ADC design include an innovative 2b/step reference scheme based on a hybrid R-2R/C-3C DAC, an interpolation-assisted time-domain 2b comparison scheme, and a TDC with dual-edge-comparison mechanism. The prototype ADC was fabricated in 0.18μm CMOS process with an active area of 0.103 mm^(2), and achieves an ENoB of 9.2 bits and an FoM of 6.7 fJ/conversion-step at 100-kS/s