Power Reductions with Energy Recovery Using Resonant Topologies

The problem of power densities in system-on-chips (SoCs) and processors has become more exacerbated recently, resulting in high cooling costs and reliability issues. One of the largest components of power consumption is the low skew clock distribution network (CDN), driving large load capacitance. This can consume as much as 70% of the total dynamic power that is lost as heat, needing elaborate sensing and cooling mechanisms. To mitigate this, resonant clocking has been utilized in several applications over the past decade. An improved energy recovering reconfigurable generalized series resonance (GSR) solution with all the critical support circuitry is developed in this work. This LC resonant clock driver is shown to save about 50% driver power (\u3e40% overall), on a 22nm process node and has 50% less skew than a non-resonant driver at 2GHz. It can operate down to 0.2GHz to support other energy savings techniques like dynamic voltage and frequency scaling (DVFS). As an example, GSR can be configured for the simpler pulse series resonance (PSR) operation to enable further power saving for double data rate (DDR) applications, by using de-skewing latches instead of flip-flop banks. A PSR based subsystem for 40% savings in clocking power with 40% driver active area reduction xii is demonstrated. This new resonant driver generates tracking pulses at each transition of clock for dual edge operation across DVFS. PSR clocking is designed to drive explicit-pulsed latches with negative setup time. Simulations using 45nm IBM/PTM device and interconnect technology models, clocking 1024 flip-flops show the reductions, compared to non-resonant clocking. DVFS range from 2GHz/1.3V to 200MHz/0.5V is obtained. The PSR frequency is set \u3e3× the clock rate, needing only 1/10th the inductance of prior-art LC resonance schemes. The skew reductions are achieved without needing to increase the interconnect widths owing to negative set-up times. Applications in data circuits are shown as well with a 90nm example. Parallel resonant and split-driver non-resonant configurations as well are derived from GSR. Tradeoffs in timing performance versus power, based on theoretical analysis, are compared for the first time and verified. This enables synthesis of an optimal topology for a given application from the GSR

Real Time Simulation and Hardware in the Loop Methods for Power Electronics Power Distribution Systems

System level testing of Power Electronics Power Distribution Systems (PEPDS) can be challenging when fine temporal resolution is required (time step below 100-200ns). In the recent years, our research group has proposed various methods to simulate in real-time PEPDS using FPGAs and time step as small as 50ns. While the proposed methods allow achieving the desired temporal resolution, they are extremely demanding in terms of resources usage and the size of the PEPDS that can be simulated on a single FPGA is strongly limited. In this dissertation -work that takes as an example application the US Navy electric Ship Zonal System (SZS)- a platform based on a commercial CPU based simulator and on a custom multi-FPGA simulator is presented. The multi-FPGA simulator enables system level PEPDS analysis while maintaining a very small-time step (70ns). Using a CPU commercial platform and multi rate execution, the power electronics part of the system is simulated together with the slow electro-mechanical portion of the PEPDS maintaining a unified vision. To achieve such a small simulation time step, the LBLMC method is applied and an innovative parallel bus interface architecture for a three FPGAs layout is introduced. The PEPDS model is decomposed for multi-FPGA executions using the nodal decomposition method. Two converters models, MMC and DAB, have been developed and included in the Open Real-Time Simulation (ORTiS) framework. To allow multi-rate execution a dedicated software and hardware interface has been developed so to interface the custom FPGA based simulator -operating with a 70ns time step- with the commercial CPU based simulator -operating at 25μs. Furthermore, to increase the flexibility and scalability of the proposed simulation platforms, a co-simulation interface based on the Aurora protocol and realizing communication between a multi-CPU and a multi-FPGA based platforms is introduced

Real-time FPGA-based co-simulation of large scale power systems

With the rapid increase of size and complexity of modem electrical power systems, 1) the simulation accuracy and 2) the capability of simulating large power systems have become two conflicting objectives. This thesis proposes a novel FPGA-RTDS co-simulator to meet these two objectives. As the basis of the co-simulator, a library of power system components is developed in FPGA, including the most commonly used power system elements and control systems. The proposed cosimulator combines the advantages of 1) the paralleled architecture, high logic density and high clock speed from FPGA and 2) better modelling flexibility and user-friendly GUI from RTDS together. Multi-FPGA structure is introduced to further improve the simulation capability for large power systems. The use of detailed EMT models in the whole system guarantees the accuracy of simulation and eliminates the potential interface error. Deeply pipelined and massively paralleled algorithms have been designed to maximize time and hardware efficiency. The modular design significantly improves the system expandability. Case studies including large scale power system with more than 4000 nodes are presented to demonstrate the simulation capability. Comparisons are made with SIMULINK and RTDS to verify the accuracy of the proposed co-simulator

Circuit and System Level Design Optimization for Power Delivery And Management

As the VLSI technology scales to the nanometer scale, power consumption has become a critical design concern of VLSI circuits. Power gating and dynamic voltage and frequency scaling (DVFS) are two effective power management techniques that are widely utilized in modern chip designs. Various design challenges merge with these power management techniques in nanometer VLSI circuits. For example, power gating introduces unique power integrity issues and trade-offs between switching noise and rush current noise. Assuring power integrity and achieving power efficiency are two highly intertwined design challenges. In addition, these trade-offs significantly vary with the supply voltage. It is difficult to use conventional power-gated power delivery networks (PDNs) to fully meet the involved conflicting design constraints while maximizing power saving and minimizing supply noise. The DVFS controller and the DC-DC power converter are two highly intertwining enablers for DVFS-based systems. However, traditional DVFS techniques treat the design optimizations of the two as separate tasks, giving rise to sub-optimal designs. To address the above research challenges, we propose several circuit and system level design optimization techniques in this dissertation. For power-gated PDN designs, we propose systemic decoupling capacitor (decap) optimization strategies that optimally trade-off between power integrity and leakage saving. First, new global decap and re-routable decap design concepts are proposed to relax the tight interaction between power integrity and leakage power saving of power-gated PDN at a single supply voltage level. Furthermore, we propose to leverage re-routable decaps to provide flexible decap allocation structures to better suit multiple supply voltage levels. The proposed strategies are implemented in an automatic design flow for choosing optimal amount of local decaps, global decaps and re-routable decaps. The proposed techniques significantly increase leakage saving without jeopardizing power integrity. The flexible decap allocations enabled by re-routable decaps lead to optimal design trade-offs for PDNs operating with two supply voltage levels. To improve the effectiveness of DVFS, we analyze the drawbacks of circuit-level only and policy-level only optimizations and the promising opportunities resulted from the cross-layer co-optimization of the DC-DC converter and online learning based DVFS polices. We present a cross-layer approach that optimizes transition time, area, energy overhead of the DC-DC converter along with key parameters of an online learning DVFS controller. We systematically evaluate the benefits of the proposed co-optimization strategy based on several processor architectures, namely single and dual-core processors and processors with DVFS and power gating. Our results indicate that the co-optimization can introduce noticeable additional energy saving without significant performance degradation

Modeling, Design and Optimization of IC Power Delivery with On-Chip Regulation

As IC technology continues to follow the Moore’s Law, IC designers have been constantly challenged with power delivery issues. While useful power must be reliably delivered to the on-die functional circuits to fulfill the desired functionality and performance, additional power overheads arise due to the loss associated with voltage conversion and parasitic resistance in the metal wires. Hence, one of the key IC power delivery design challenges is to develop voltage conversion/regulation circuits and the corresponding design strategies to provide a guaranteed level of power integrity while achieving high power efficiency and low area overhead. On-chip voltage regulation, a significant ongoing design trend, offers appealing active supply noise suppression close to the loads and is well positioned to address many power delivery challenges. However, to realize the full potential of on-chip voltage regulation requires systemic optimization of and tradeoffs among settling time, steady-state error, power supply noise, power efficiency, stability and area overhead, which are the key focuses of this dissertation. First, we develop new low-dropout voltage regulators (LDOs) that are well optimized for low power applications. To this end, dropout voltage, bias current and speed are important competing design objectives. This dissertation presents new flipped voltage follower (FVF) based topologies of on-chip voltage regulators that handle ultra-fast load transients in nanoseconds while achieving significant improvement on bias current consumption. An active frequency compensation is embedded to achieve high area efficiency by employing a smaller amount of compensation capacitors, the major silicon area contributor. Furthermore, in one of the proposed topologies an auxiliary digital feedback loop is employed in order to lower quiescent power consumption further. Second, coping with supply noise is becoming increasingly more difficult as design complexity grows, which leads to increased spatial and temporal load heterogeneity, and hence larger voltage variations in a given power domain. Addressing this challenge through a distributed methodology wherein multiple voltage regulators are placed across the same voltage domain is particularly promising. This distributive nature allows for even faster suppression of multiple hot spots by the nearby regulators within the power domain and can significantly boost power integrity. Nevertheless, reasoning about the stability of such distributively regulated power networks becomes rather complicated as a result of complex interactions between multiple active regulators and the large passive subnetwork. Coping with this stability challenge requires new theory and stability-ensuring design practice, as targeted by this dissertation. For the first time, we adopt and develop a hybrid stability framework for large power delivery networks with distributed voltage regulation. This framework is local in the sense that both the checking and assurance of network stability can be dealt with on the basis of each individual voltage regulator, leading to feasible design of large power delivery networks that would be computationally impossible otherwise. Accordingly, we propose a new hybrid stability margin concept, examine its tradeoffs with power efficiency, supply noise and silicon area, and demonstrate the resulted key design implications pertaining to new stability-ensuring LDO circuit design techniques and circuit topologies. Finally, we develop an automated hybrid stability design flow that is computationally efficient and provides a practical guarantee of network stability

A Holistic Approach to Functional Safety for Networked Cyber-Physical Systems

Functional safety is a significant concern in today's networked cyber-physical systems such as connected machines, autonomous vehicles, and intelligent environments. Simulation is a well-known methodology for the assessment of functional safety. Simulation models of networked cyber-physical systems are very heterogeneous relying on digital hardware, analog hardware, and network domains. Current functional safety assessment is mainly focused on digital hardware failures while minor attention is devoted to analog hardware and not at all to the interconnecting network. In this work we believe that in networked cyber-physical systems, the dependability must be verified not only for the nodes in isolation but also by taking into account their interaction through the communication channel. For this reason, this work proposes a holistic methodology for simulation-based safety assessment in which safety mechanisms are tested in a simulation environment reproducing the high-level behavior of digital hardware, analog hardware, and network communication. The methodology relies on three main automatic processes: 1) abstraction of analog models to transform them into system-level descriptions, 2) synthesis of network infrastructures to combine multiple cyber-physical systems, and 3) multi-domain fault injection in digital, analog, and network. Ultimately, the flow produces a homogeneous optimized description written in C++ for fast and reliable simulation which can have many applications. The focus of this thesis is performing extensive fault simulation and evaluating different functional safety metrics, \eg, fault and diagnostic coverage of all the safety mechanisms

Modular platform for research in microgrids

The present Ph.D. thesis has been developed following an Industrial Ph.D. program and verses on developing a commercial piece of equipment for teknoCEA, a spin-off company from CITCEA-UPC. The thesis is centered on developing power electronics-based emulation systems for research in microgrids. Lately, the use of power electronics-based emulation systems is drawing substantial attention in the field of microgrids because their characteristics substantially facilitate research in laboratory facilities. First, the suitability of different topologies for implementing an emulation platform is analyzed. The focus is set on the topologies adjustability to implement various types of emulation systems. The analysis determines the most appropriate number of legs for the platform. A comparative analysis is done between two-level and multi-level topologies to determine their suitability based on different aspects. Moreover, the analysis confirms the usefulness of wide-bandgap semiconductors for this type of application. Next, a control structure is proposed together with its implementation in a low-cost microcontroller based on a modular software architecture. The control strategy based on fractional proportional resonant controllers for AC emulation systems provides a control system with high control bandwidth while keeping a low computational cost. The control strategy for DC emulation systems is provided to reach a fast transient response and immunity to external disturbances, which is key for good emulation of electric systems. The modular software architecture provides a software framework easily adjustable to the needs of multiple emulation systems. That allows the implementation of the multiple control strategies with minimum changes. Additionally provides a graphical representation of the software architecture from a static and dynamic point of view. Last, the reliability of the proposed platform is assessed based on the reliability curves provided in the literature. The reliability analysis is centered on the semiconductors and capacitors. It provides evidence that emulation systems typical currents and voltages clearly affect their reliability. For the capacitors reliability assessment, a thermal modeling methodology is proposed to overcome the limitations of standard approximations. The methodology is based on anisotropic modeling of the capacitor winding. Finally, the reliability analysis establishes the guidelines to assess the platform reliability if a given mission profile is provided.La present tesi doctoral s'ha dut a terme seguint un programa de doctorat industrial. La tesi exposa el desenvolupament d'un equip comercial per a teknoCEA, una spin-off del CITCEA-UPC. La tesi es centra en el desenvolupament d'emuladors basats en electrònica de potència per recerca en el camp de les microxarxes. Darrerament, l'ús d'emuladors s'ha estès ja que les seves característiques faciliten molt la recerca en laboratoris. En primer lloc, s'analitza la idoneïtat de diferents topologies per implementar una plataforma d'emulació. El focus recau en la capacitat de diferents topologies per ajustar-se a la implementació de múltiples sistemes d'emulació. L'anàlisi determina el número òptim de branques. Un anàlisi comparatiu entre topologies dos nivells i multinivell permet determinar-ne la idoneïtat en funció de diferents aspectes. A continuació, es proposa una estructura de control juntament amb la seva implementació en un microcontrolador de baix cost a partir d'una arquitectura de programari modular. L'estratègia de control basada en controladors FPR (fractional proportional resonant) per a emuladors de corrent altern, proporciona un sistema de control amb un gran ample de banda amb un baix cost computacional. L'estratègia de control proposada per emuladors de corrent continu proporciona una resposta transitòria ràpida i elevada immunitat a pertorbacions, aspecte clau per a una bona emulació de sistemes elèctrics. L'arquitectura de programari modular proporciona un marc de programari fàcilment ajustable a les necessitats de múltiples emuladors. Això permet la implementació de les múltiples estratègies de control amb canvis mínims. A més, ofereix una representació gràfica de l'arquitectura del programari tant des d'un punt de vista estàtic com dinàmic. Finalment, s'avalua la fiabilitat de la plataforma a partir de les corbes de fiabilitat disponibles a la bibliografia científica. L'anàlisi es centra en els semiconductors i condensadors i proporciona evidència que els corrents i les tensions típics en emuladors afecten la seva fiabilitat. Per a l'avaluació de la fiabilitat dels condensadors, es proposa una metodologia de modelització tèrmica que permet superar les limitacions de les metodologies emprades típicament en la bibliografia científica. La metodologia es basa en el modelatge del bobinat del condensador com un element anisòtrop. Per últim, l'anàlisi de fiabilitat estableix les pautes per avaluar la fiabilitat de la plataforma en el cas que es proporcioni un perfil d'operació determinat.Postprint (published version

Advanced sensors technology survey

This project assesses the state-of-the-art in advanced or 'smart' sensors technology for NASA Life Sciences research applications with an emphasis on those sensors with potential applications on the space station freedom (SSF). The objectives are: (1) to conduct literature reviews on relevant advanced sensor technology; (2) to interview various scientists and engineers in industry, academia, and government who are knowledgeable on this topic; (3) to provide viewpoints and opinions regarding the potential applications of this technology on the SSF; and (4) to provide summary charts of relevant technologies and centers where these technologies are being developed

Efficient and Scalable Computing for Resource-Constrained Cyber-Physical Systems: A Layered Approach

With the evolution of computing and communication technology, cyber-physical systems such as self-driving cars, unmanned aerial vehicles, and mobile cognitive robots are achieving increasing levels of multifunctionality and miniaturization, enabling them to execute versatile tasks in a resource-constrained environment. Therefore, the computing systems that power these resource-constrained cyber-physical systems (RCCPSs) have to achieve high efficiency and scalability. First of all, given a fixed amount of onboard energy, these computing systems should not only be power-efficient but also exhibit sufficiently high performance to gracefully handle complex algorithms for learning-based perception and AI-driven decision-making. Meanwhile, scalability requires that the current computing system and its components can be extended both horizontally, with more resources, and vertically, with emerging advanced technology. To achieve efficient and scalable computing systems in RCCPSs, my research broadly investigates a set of techniques and solutions via a bottom-up layered approach. This layered approach leverages the characteristics of each system layer (e.g., the circuit, architecture, and operating system layers) and their interactions to discover and explore the optimal system tradeoffs among performance, efficiency, and scalability. At the circuit layer, we investigate the benefits of novel power delivery and management schemes enabled by integrated voltage regulators (IVRs). Then, between the circuit and microarchitecture/architecture layers, we present a voltage-stacked power delivery system that offers best-in-class power delivery efficiency for many-core systems. After this, using Graphics Processing Units (GPUs) as a case study, we develop a real-time resource scheduling framework at the architecture and operating system layers for heterogeneous computing platforms with guaranteed task deadlines. Finally, fast dynamic voltage and frequency scaling (DVFS) based power management across the circuit, architecture, and operating system layers is studied through a learning-based hierarchical power management strategy for multi-/many-core systems