Design of low-voltage operational amplifier

Práce se zabývá návrhem nízkonapěťového operačního zesilovače. V první části práce jsou uvedeny teoretické poznatky týkající se technologie CMOS a MOSFET tranzistoru. V další části jsou popsány jednotlivé techniky používané při návrhu nízkonapěťových obvodů. Následně je navržen dvoustupňový bulk-driven operační transkonduktanční zesilovač. Toto zapojení je následně rozšířeno na DDA zesilovač, na kterém je demonstrována aplikace přístrojového zesilovače.The work deals with design of low-voltage operational amplifier. First part presents theoretical knowledge of CMOS technology and MOSFET transistor. The next part describes low-voltage techniques used in low-voltage circuits. Transconductance operational amplifier based on bulk-driven technique is designed. This circuit is then enhanced into DDA, that demonstrates application as instrumentation amplifier.

The Effect Of Hot Carrier Stress On Low Noise Amplifier Radio Frequency Performance Under Weak And Strong Inversion

This thesis work is mainly focused on studying RF performance degradation of a low noise amplifier (LNA) circuit due to hot carrier effect (HCE) in both the weak and strong inversion regions. Since the figures of merit for the RF circuit characterization are gain, noise figure, input, and output matching, the LNA RF performance drift is evaluated in a Cadence SpectreRF simulator subject to these features. This thesis presents hot carrier induced degradation results of an LNA to show that the HCE phenomenon is one of the serious reliability issues in the aggressively scaled RF CMOS design, especially for long-term operation of these devices. The predicted degradation from simulation results can be used design reliable CMOS RF circuits

Low Power Demodulator Design for RFID Applications

Power consumption is a key issue in today\u27s digital and analog design for various portable devices. Radio frequency identification (RFID) is a technology which requires very low power and it uses electromagnetic waves in the radio frequency to transmit the ID of objects. It has a broad range of uses although inventory management and tracking are the most common. A low power demodulator, part of a RFID transponder operating in the 900 MHz range, is presented using sub-threshold design. Using this technique and working with 90 nm complementary metal-oxide-semiconductor (CMOS) technology, the circuit can operate with a supply voltage as low as 0.3 V, consuming a very small amount of power compared to other demodulators in the literature, making it suitable for ultra-low power applications

New Possibilities In Low-voltage Analog Circuit Design Using Dtmos Transistors

(Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2013(PhD) -- İstanbul Technical University, Institute of Science and Technology, 2013Bu çalışmada DTMOS yaklaşımı çok düşük besleme gerilimlerinde çalışan çok düşük güç tüketimli devrelere başarıyla uygulanmıştır. Tasarlanan devreler arasında OTA, OP-AMP, CCII gibi analog aktif yapı blokları, çarpma devresi, sadece-MOS yapılar gibi devreler bulunmaktadır. Tasarlanan devreler SPICE benzetimleri ile doğrulanmıştır. İleri yönde gövde kutuplamaya bağlı olarak DTMOS transistorun yapısından kaynaklanan, efektif olarak düşük eşik gerilimli çalışma özelliği nedeniyle, çok düşük güç tüketimli ve çok düşük gerilimli devrelerde DTMOS yaklaşımının geçerli bir alternatif olduğu bu çalışmayla gösterilmiştir. DTMOS yaklaşımının geniş bir alanda çeşitlilik gösteren analog devre yapılarında çok düşük besleme gerilimlerinde bile kabul edilebilir bir performansla kullanılabileceği bulunmuştur.In this study, DTMOS approach to the design of ultra low-voltage and ultra low-power analog circuits, has been successfully applied to the circuits ranging from EEG filtering circuits, speech processing filters in hearing aids, multipliers, analog active building blocks: OTA, OP-AMP, CCII to MOS-only circuits. The proposed circuits are verified with SPICE simulations. It is found that in designing ultra low-voltage, ultra low-power analog circuits, DTMOS approach is a viable alternative due to its inherent characteristic of effective low threshold voltage behaviour under forward body bias. This approach can be applied to several analog application subjects with acceptable performance under even ultra low supply voltages.DoktoraPh

Projeto de um LNA para aplicações ZigBee e sua adequação para o uso em internet das coisas

Trabalho de Conclusão de Curso (graduação)—Universidade de Brasília, Faculdade UnB Gama (FGA), Engenharia Eletrônica, 2019.A interação possibilitada pela comunicação entre dispositivos e usuários via protocolos de rede, tais como ZigBee, Bluetooth e WiFi, tem proporcionado maiores funcionalidades, comodidades e portabilidade ao usuário final, principais pilares do conceito Internet of Things (IoT). Para que isso seja possível, é necessário o projeto de sistemas de comunicações de baixo custo e consumo energético, tornando factível a produção em larga escala de objetos inteligentes, requisitos que podem ser atendidos por meio do protocolo ZigBee. Apartir da análise de diversos sistemas de transcepção Zigbee já existentes, esse trabalho apresenta comparações entre topologias de um Front-end de recepção Zigbee e propõe uma topologia de LNA com foco em otimização em termos de área consumida no chip e eficiência energética, garantindo assim, uma redução no custo de produção em larga escala e sua adequação às aplicações que envolvem o conceito de Internet das Coisas (IoT). A metodologia irá se basear no conceito de fluxo de projeto Bottom-up, apartir da qual será proposto um Low Noise Amplifier (LNA) para transceptores ZigBee com a tecnologia CMOS de 130 nm, operando na região sub-limiar. Será apresentada uma metodologia de projeto para seu desenvolvimento, desde sua modelagem analítica, até sua concepção à nível de hardware. Os resultados são analisados por meio de gráficos e tabelas comparativas de simulações e verificações paramétricas no software Virtuoso, da Cadence.The interaction enabledby the communication between devices and users via network protocols, such as ZigBee, Bluetooth and WiFi, has provided greater functionalities, confort and portability to the end user, main pillars of the concept of Internet of Things (IoT). For this to be possible, it is necessary to design low-cost and energy-efficient communications systems, making feasible the large-scale production of intelligent objects, requirements that can be met through the ZigBee protocol. Based on the analysis of existing ZigBee transceivers, this work presents comparisons between topologies of a front-end receiver and presents an LNA topology with focus in terms of chip area consumption and energy efficiency, thus guaranteeing a reduction in cost of large-scale production and its suitability for applications in the Internet of Things (IoT) concept. The methodology will be a bottom-up design flow based in ZigBee transceivers with 130 nm CMOS technology, operating in the sub-threshold region. It will be preented a methodology for its development, from the analytical modeling to its hardware level implementation. The results will be analyzed through graphs and comparative tables, containing information about all simulations and parametric verifications made in Cadence’s Virtuoso software

Conception et caractérisation d'une puce colorimétrique pour la détection des allergènes

This PhD treats a multidisciplinary subject based on the design of a biological micro-sensor prototype for the detection of antibodies of patients susceptible to be allergic.The goal has been the miniaturization of the ELISA "Enzyme Linked Immune Sorbent Assay" method, designing in integrated full-custom colorimetric sensor with a CMOS APS technology. This sensor is installed below a microfluidic system containing the biological test sample, the whole is illuminated via an optical fiber. The sensor detects the light passed through the micro reservoir containing the sample, the induced photo-currents is related to the concentration of the solution. The color change of the enzyme reaction due to the presence of antibodies in the serum, and the quantitative evaluation of the concentration will be determined by the measurement of the induced photo-currents. The sensor may contain a matrix of 20x20 color detector pixels and their reading and control electronics. For cost reasons, we validated the method using a matrix of 4 x 4 pixels of color detectors.The design of electrical device was followed by a colorimetric and electrical characterizations. The latter was used to validate the operation of the control block of the circuit as well as that of the pixel (readout electronics, BDJ). The results brought by measurements are in good agreement with those obtained through simulations. The colorimetric characterization consists in measuring the intensity of the color of two different solutions of different colors. These measurements have shown that our sensor is more sensitive than a spectrometer. Therefore, this research work has contributed to the miniaturization of a colorimetric sensor and its electronic part for the Immunoassay based on the ELISA method.Cette thèse traite un sujet pluridisciplinaire, la conception d’un prototype de micro-capteur biologique pour la détection des anticorps de patients susceptibles d'être allergiques.Elle a pour objectif la miniaturisation de la méthode ELISA pour « Enzyme Linked Immune Sorbent Assay » en concevant en « full-custom », avec une technologie CMOS APS, un capteur colorimétrique. Ce capteur est posé en dessous un système micro fluidique contenant l’échantillon biologique à tester, le tout est illuminé via une fibre optique. Le détecteur capte la lumière qui a traversé le micro-tube contenant l’échantillon. Les courants photoniques induits sont liés à la concentration et la coloration de la solution. Le virage colorimétrique de la réaction enzymatique, due à la présence des anticorps dans le sérum, et l’évaluation quantitative de la concentration seront déterminée par la mesure de ces photo-courants. Le capteur pourrait contenir une matrice de 20x20 pixels de détecteurs de couleur ainsi que leur électronique de lecture et de commande. Pour des raisons de coûts, nous avons validé le procédé à l’aide d’une matrice de 4x4 pixels de détecteur de couleur. La réalisation du circuit a été suivie par une caractérisation électrique et colorimétrique. La caractérisation électrique a permis de valider le fonctionnement du bloc de commande du circuit ainsi que celui du pixel (l’électronique de lecture, BDJ). Les résultats de mesures concordent avec ceux de simulations. La caractérisation colorimétrique consiste à mesurer le virage colorimétrique de deux solutions différentes. Les mesures ont pu montrer que notre capteur est plus sensible que le spectromètre utilisé pour mesurer la concentration des deux solutions. Ainsi ce travail de recherche a contribué à la miniaturisation d’une bio-puce colorimétrique dédiée aux tests immunologiques basée sur la méthode ELISA

Energy Efficiency in Communications and Networks

The topic of "Energy Efficiency in Communications and Networks" attracts growing attention due to economical and environmental reasons. The amount of power consumed by information and communication technologies (ICT) is rapidly increasing, as well as the energy bill of service providers. According to a number of studies, ICT alone is responsible for a percentage which varies from 2% to 10% of the world power consumption. Thus, driving rising cost and sustainability concerns about the energy footprint of the IT infrastructure. Energy-efficiency is an aspect that until recently was only considered for battery driven devices. Today we see energy-efficiency becoming a pervasive issue that will need to be considered in all technology areas from device technology to systems management. This book is seeking to provide a compilation of novel research contributions on hardware design, architectures, protocols and algorithms that will improve the energy efficiency of communication devices and networks and lead to a more energy proportional technology infrastructure

Analog Circuit Design in PD-SOI CMOS Technology for High Temperatures up to 400°C using Reverse Body Biasing (RBB)

This work focuses on analog integrated CMOS (Complementary Metal-Oxide-Semiconductor) circuit design in SOI (Silicon on Insulator) technology for the use in high temperature applications. It investigates the influence of reverse body biasing (RBB) on the analog characteristics of SOI-MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) transistors. Additionally, the enhancement of the operation capability of fundamental analog circuits at high temperatures up to 400°C with the use of RBB is investigated. Analog and digital integrated circuits are used in a variety of applications, e.g. consumer electronics or industrial measurement equipment. These integrated circuits have to work properly in the temperature range predefined by the application. As an example, operating temperatures reaching from −50°C to 250°C are required for geothermal drilling applications. Currently in the automotive industry, electronics have to operate reliably up to 150°C and as control electronics are placed closer to the engine, a much higher operating temperature is required. High temperature electronics are also used in avionic- and space applications, e.g. for future Venus exploration missions, where they have to withstand operating temperatures of 300°C to 500°C. Active or passive cooling of electronic components requires additional space and weight that increases the cost of the overall system. Cooling can be avoided in case electronics are capable of operating in harsh environmental conditions, i.e. at high temperatures. SOI-MOSFET devices are theoretically capable of operation up to 400°C or even higher, depending on the doping concentration of the silicon film. Nearly all material and device properties of importance to electronics worsen with increasing temperature, which is why 300°C to 350°C is the currently stated experimental maximum operating temperature of SOI devices. Analog circuit design up to the theoretical temperature limit exhibits severe limitations as SOI-MOSFET device characteristics are degenerated. SOI-MOSFET devices are partially depleted (PD) or fully depleted (FD), depending on the temperature, doping concentration of the silicon film, silicon film thickness and also channel length. FD devices offer a much better analog performance compared to their partially depleted counterparts and are preferred for analog circuit design. In the considered SOI technology, SOI- MOSFET devices are FD at low temperatures and PD at high temperatures. The transition from FD to PD at high temperatures leads to increased device leakage currents and hence reduces the overall performance of the transistor devices. Thereby, the gm/Id factor as a major figure of merit is decreased dramatically at high temperatures. Especially the moderate inversion region, which offers high intrinsic gain and moderate intrinsic bandwidth, is strongly affected as device leakage currents exceed the range of device operating currents at high temperatures. Reverse body biasing (RBB) refers to the reverse biasing of the film-source PN-junction of a MOSFET transistor. In recent works, reverse body biasing has been applied to digital circuits in order to reduce the static current consumption. Reverse body biasing has also been investigated in the analog domain. Nevertheless, the importance of the technique to realize analog circuits capable of operating at the theoretical temperature limit of SOI technology has not been identified yet. SOI-MOSFET devices with an H-shaped gate are investigated in a 1.0 µm PD-SOI technology. These devices provide a body-contact, which is used to apply the reverse body bias. It is found that due to the use of RBB, these devices remain fully depleted in the considered temperature range up to 400°C. Due to the reduction of leakage currents, reverse biased SOI-MOSFET devices are capable of operating in the mid moderate inversion region, with an operating current of one fifth of the leakage current level which was measured without RBB. This results in an improved gm/Id factor and an increase of the intrinsic gain by approximately 14 dB. Besides the investigation of SOI-MOSFET device characteristics, reverse body biasing is also applied to fundamental analog building blocks, e.g. an analog switch, current mirrors, a two-stage operational amplifier and a first order bandgap voltage reference. It is found that reverse body biasing significantly improves the high temperature operation of these circuits. In summary, the proposed technique of reverse body biasing offers the possibility to achieve FD device characteristics in a PD-SOI technology and thereby to improve the performance of analog circuits at high temperatures up to 400°C.Die vorliegende Arbeit ist im Bereich der analogen, integrierten CMOS (Complementary Metal-Oxide-Semiconductor) Schaltungstechnik in SOI (Silicon on Insulator) Technologie für den Einsatz in Hochtemperaturanwendungen angesiedelt. Ausgehend von der Untersuchung analoger Transistoreigenschaften von SOI-MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) Transistoren unter Verwendung von RBB (Reverse body biasing), wird zusätzlich die verbesserte Hochtemperaturtauglichkeit grundlegender analoger Schaltungen bis 400°C unter dem Einfluss von RBB untersucht. Analoge und digitale integrierte Schaltungen werden in einer Vielzahl von Anwendungen, wie z. B. in der Unterhaltungselektronik oder der industriellen Messtechnik eingesetzt. Dabei müssen diese Schaltungen in dem für die Anwendung spezifizierten Temperaturbereich zuverlässig arbeiten. Beispielsweise werden elektronische Bauelemente in einem Temperaturbereich von −50°C bis 250°C zur Durchführung geo-thermischer Bohrungen eingesetzt. In der Automobilindustrie müssen integrierte Schaltungen bis zu einer Temperatur von 150°C zuverlässig arbeiten, wobei durch die Platzierung der Steuerelektronik in unmittelbarer Nähe zum Motor künftig weiter steigende Betriebstemperaturen erforderlich werden. Die Hochtemperaturelektronik findet ebenfalls Anwendung in der Luft- und Raumfahrt. Bei der zukünftigen Erkundung der Venus beispielsweise, müssen Umgebungstemperaturen von 300°C-500°C von allen Systemkomponenten unbeschadet überstanden werden. Die aktive oder passive Kühlung integrierter, elektronischer Komponenten erfordert zusätzlich Platz und Gewicht, und erhöht somit die Kosten des Gesamtsystems. Dabei kann die Kühlung elektronischer Komponenten vermieden werden, wenn diese in der Lage sind, bei hohen Umgebungstemperaturen zu arbeiten. SOI-MOSFET Transistoren können theoretisch bei Umgebungstemperaturen bis zu 400°C und höher betrieben werden. Diese Temperaturobergrenze wird stark durch die Dotierstoffkonzentration im Siliziumfilm und der Siliziumfilmdicke bestimmt. Da nahezu alle wesentlichen Material- und Leistungseigenschaften integrierter Schaltungen durch steigende Umgebungstemperaturen negativ beeinflusst werden, liegt die momentane Temperaturobergrenze von SOI-basierten Hochtemperaturschaltungen im Bereich der praktischen Anwendung daher lediglich bei 300°C bis 350°C. Somit werden die Möglichkeiten zur Realisierung integrierter Schaltungen über diese Grenze hinaus durch die Degeneration der Transistoreigenschaften bei hohen Temperaturen limitiert. Abhängig von der Temperatur, der Dotierstoffkonzentration im Siliziumfilm, der Siliziumfilmdicke und der Kanallänge, sind die Transistoren teilweise verarmt (partially depleted, PD) oder vollständig verarmt (fully depleted, FD). FD Transistoren weisen deutlich verbesserte Analogeigenschaften auf als PD Transistoren und werden aus diesem Grund bevorzugt eingesetzt. In der untersuchten SOI Technologie ändern SOI-MOSFET Transistoren ihren Verarmungszustand von FD bei niedrigen Temperaturen zu PD bei hohen Temperaturen. Der Zustand der teilweisen Verarmung führt zum Anstieg von Leckströmen innerhalb der Transistoren und damit zur Degeneration der analogen Transistoreigenschaften. Reverse body biasing bezeichnet den Betrieb von MOSFET Transistoren mit einem in Sperrrichtung betriebenen Film-Source PN-Übergang. In bisherigen Arbeiten wurde RBB dazu eingesetzt, das Leckstromverhalten digitaler integrierter Schaltungen zu verbessern und unter anderem um die Durchbruchspannung der Transistoren zu beeinflussen. Die Auswirkungen dieser Methode auf die analogen Eigenschaften von SOI-MOSFET Transistoren und den Betrieb analoger Schaltungen bei hohen Temperaturen wurden jedoch bislang nicht ausreichend untersucht. In dieser Arbeit werden HGATE SOI-MOSFET Transistoren in einer 1.0 µm PD-SOI CMOS Technologie untersucht. Diese Transistoren zeichnen sich durch eine H-förmige Gate-Elektrode sowie einen separaten Filmkontakt aus, welcher zur Anwendung von RBB verwendet wird. Es zeigt sich, dass der Verarmungszustand der Transistoren durch die Anwendung von RBB bei hohen Temperaturen positiv beeinflusst werden kann. So bleiben die untersuchen Transistoren im betrachteten Temperaturbereich bis 400°C vollständig verarmt. Durch die deutliche Reduzierung der Leckströme ist es möglich, die Transistoren bis 400°C im Arbeitspunkt der moderaten Inversion zu betreiben. Dabei kann der Betriebsstrom der Transistoren bis auf ein Fünftel des vorherigen Leckstromniveaus reduziert werden, was zu einer wesentlichen Verbesserung des gm/Id Faktors und einem Anstieg der intrinsischen Verstärkung um ca. 14 dB führt. Neben der Untersuchung der SOI-MOSFET Transistoreigenschaften wurde zudem der Einfluss von RBB auf die Hochtemperaturtauglichkeit grundlegender analoger Schaltungsblöcke, wie z. B. analoger Schalter, Stromspiegel, zweistufiger Operationsverstärker und Bandgap Spannungsreferenzen untersucht. Es zeigt sich, dass sich die Hochtemperaturtauglichkeit dieser Schaltungen durch den Einsatz von RBB maßgeblich verbessern lässt. Zusammengefasst werden durch die Anwendung von RBB in einer PD-SOI Technologie FD-SOI Transistoreigenschaften erzielt, die den Betrieb analoger Schaltungen bis 400°C ermöglichen