A versatile CMOS transistor array IC for the statistical characterization of time-zero variability, RTN, BTI, and HCI

Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 x 1800 µm²

A detailed study of the gate/drain voltage dependence of RTN in bulk pMOS transistors

Random Telegraph Noise (RTN)has attracted increasing interest in the last years. This phenomenon introduces variability in the electrical properties of transistors, in particular in deeply-scaled CMOS technologies, which can cause performance degradation in circuits. In this work, the dependence of RTN parameters, namely current jump amplitude and emission and capture time constants, on the bias conditions, both VG and VD, has been studied on a set of devices, with a high granularity in a broad voltage range. The results obtained for the VG dependences corroborate previous works, but suggest a unique trend for all the devices in a VG range that goes from the near-threshold region up to voltages over the nominal operation bias. However, different trends have been observed in the parameters dependence for the case of VD. From the experimental data, the probabilities of occupation of the associated defects have been evaluated, pointing out large device-to-device dispersion in the VD dependences.Ministerio de Ciencia, Innovación y Universidades TEC2016-75151-C3-R, BES-2017-08016

A versatile CMOS transistor array IC for the statistical characterization of time-zero variability, RTN, BTI, and HCI

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 x 1800 µm².Peer ReviewedPostprint (author's final draft

Combined C-V/I-V and RTN CMOS Variability Characterization Using An On-Chip Measurement System

With the number of transistors integrated into a single integrated circuit (IC) crossing the one-billion mark and complementary metal-oxide-semiconductor (CMOS) technology scaling pushing device dimensions ever-so-close to atomic scales, variability in transistor performance is becoming the dominant constraint in modern-day CMOS IC design. Developing novel approaches for device characterization, which allow a detailed study of electrical transistor characteristics across large statistical sample sets, is crucial for the proper identification, characterization, and modeling of different physical sources of device variability. On-chip characterization methodologies have the potential to address all of these issues by enabling the characterization of large statistical device sample sets, while also allowing for high measurement quality and throughput. In this work, a fully-integrated system for on-chip combined capacitance-voltage (C-V) and current-voltage (I-V) characterization of a large integrated test transistor array implemented in a 45-nm bulk CMOS process is presented. On-chip I-V characterization is implemented using a four-point Kelvin measurement technique with 12-bit sub-10 nA current measurement resolution, 10-bit sub-1 mV voltage measurement resolution, and sampling speeds on the order of 100 kHz. C-V characterization is performed using a novel leakage- and parasitics-insensitive charge-based capacitance measurement (CBCM) technique with atto-Farad resolution. The on-chip system is employed in developing a comprehensive CMOS transistor variability characterization methodology, studying both random and systematic sources of quasi-static device variability. For the first time, combined C-V/I-V characterization of circuit-representative devices is demonstrated and used to extract variations in the under- lying physical parameters of the device. Additionally, the fast current sampling capabilities of the system are used for the characterization of random telegraph noise (RTN) in small area devices. An automated methodology for the extraction of RTN parameters is developed, and the statistics of RTN are studied across device type, bias, and geometry

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Characterizationof FD-SOI transistor

In this project, measurements have been made on FD-SOI transistors, fabricated by CEA-LETI, to carry out a characterization of these devices, since they are very new and need to be studied. This work has focused on characterizing the aging mechanism of the devices and the observed RTN. To characterize the aging mechanism and variability of the samples based on the applied cycles, the measurements have been made by applying constant stress voltages (CVS) directly to the device with a wafer prove station and a semiconductor parameter analyzer (SPA). To observe TN, different electrical procedures have been studied, controlling the different parameters during the measurements.En aquest projecte s'han realitzat mesures en transistors FD-SOI, fabricats per CEA-LETI, per tal de dur a terme una caracterització d'aquests dispositius, ja que són molt nous i necessiten de ser estudiats. Aquest treball s'ha centrat en caracteritzar l'envelliment dels dispositius i el RTN observat. Per a caracteritzar l'envelliment i la variabilitat de les mostres en funció dels cicles aplicats, les mesures s'han realitzat aplicant tensions d'estrés constant (CVS) directament al dispositiu amb una taula de puntes i un analitzador de paràmetres de semiconductors (SPA). Per tal d'observar RTN s'han estudiat diferents procediments elèctrics, controlant els diferents paràmetres durant les mesures.En este proyecto se han realizado medidas en transistores FD-SOI, fabricados por CEA-LETI, para llevar a cabo una caracterización de estos dispositivos, puesto que son muy nuevos y necesitan de ser estudiados. Este trabajo se ha centrado en caracterizar los mecanismos de envejecimiento de los dispositivos y el RTN observado. Para caracterizar el envejecimiento y la variabilidad de las muestras en función de los ciclos aplicados, las medidas se han realizado aplicando tensiones de estrés constante (CVS) directamente al dispositivo con una tabla de puntas y un analizador de parámetros de semiconductores (SPA). Para observar RTN se han estudiado diferentes procedimientos eléctricos, controlando los diferentes parámetros durante las medidas

ランダム・テレグラフ・ノイズの微細MOSFETへの影響に関する研究

筑波大学 (University of Tsukuba)201

Stochastic Memory Devices for Security and Computing

With the widespread use of mobile computing and internet of things, secured communication and chip authentication have become extremely important. Hardware-based security concepts generally provide the best performance in terms of a good standard of security, low power consumption, and large-area density. In these concepts, the stochastic properties of nanoscale devices, such as the physical and geometrical variations of the process, are harnessed for true random number generators (TRNGs) and physical unclonable functions (PUFs). Emerging memory devices, such as resistive-switching memory (RRAM), phase-change memory (PCM), and spin-transfer torque magnetic memory (STT-MRAM), rely on a unique combination of physical mechanisms for transport and switching, thus appear to be an ideal source of entropy for TRNGs and PUFs. An overview of stochastic phenomena in memory devices and their use for developing security and computing primitives is provided. First, a broad classification of methods to generate true random numbers via the stochastic properties of nanoscale devices is presented. Then, practical implementations of stochastic TRNGs, such as hardware security and stochastic computing, are shown. Finally, future challenges to stochastic memory development are discussed

True random number generator based on the variability of the high resistance state of RRAMs

Hardware-based security primitives like True Random Number Generators (TRNG) have become a crucial part in protecting data over communication channels. With the growth of internet and cloud storage, TRNGs are required in numerous cryptographic operations. On the other hand, the inherently dense structure and low power characteristics of emerging nanoelectronic technologies such as resistive-switching memories (RRAM) make them suitable elements in designing hardware security modules integrated in CMOS ICs. In this paper, a memristor based TRNG is presented by leveraging the high stochasticity of RRAM resistance value in OFF (High Resistive) state. In the proposal, one or two devices can be used depending on whether the objective is focused on saving area or obtaining a higher random bit frequency generation. The generated bits, based on a combination of experimental measurements and SPICE simulations, passed all 15 National Institute of Standards and Technology (NIST) tests and achieved a throughput of tens of MHz.Postprint (published version