Modeling and analysis of semiconductor manufacturing processes using petri nets

This thesis addresses the issues in modeling and analysis of multichip module (MCM) manufacturing processes using Petri nets. Building such graphical and mathematical models is a crucial step to understand MCM technologies and to enhance their application scope. In this thesis, the application of Petri nets is presented with top-down and bottom-up approaches. The theory of Petri nets is summarized with its basic notations and properties at first. After that, the capability of calculating and analyzing Petri nets with deterministic timing information is extended to meet the requirements of the MCM models. Then, using top-down refining and system decomposition, MCM models are built from an abstract point to concrete systems with timing information. In this process, reduction theory based on a multiple-input-single-output modules for deterministic Petri nets is applied to analyze the cycle time of Petri net models. Besides, this thesis is of significance in its use of the reduction theory which is derived for timed marked graphs - an important class of Petri nets

Development and Packaging of Microsystems Using Foundry Services

Micro-electro-mechanical systems (MEMS) are a new and rapidly growing field of research. Several advances to the MEMS state of the art were achieved through design and characterization of novel devices. Empirical and theoretical model of polysilicon thermal actuators were developed to understand their behavior. The most extensive investigation of the Multi-User MEMS Processes (MUMPs) polysilicon resistivity was also performed. The first published value for the thermal coefficient of resistivity (TCR) of the MUMPs Poly 1 layer was determined as 1.25 x 10(exp -3)/K. The sheet resistance of the MUMPs polysilicon layers was found to be dependent on linewidth due to presence or absence of lateral phosphorus diffusion. The functional integration of MEMS with CMOS was demonstrated through the design of automated positioning and assembly systems, and a new power averaging scheme was devised. Packaging of MEMS using foundry multichip modules (MCMs) was shown to be a feasible approach to physical integration of MEMS with microelectronics. MEMS test die were packaged using Micro Module Systems MCM-D and General Electric High Density Intercounect and Chip-on-Flex MCM foundries. Xenon difluoride (XeF2) was found to be an excellent post-packaging etchant for bulk micromachined MEMS. For surface micromachining, hydrofluoric acid (HF) can be used

Materials for high-density electronic packaging and interconnection

Electronic packaging and interconnections are the elements that today limit the ultimate performance of advanced electronic systems. Materials in use today and those becoming available are critically examined to ascertain what actions are needed for U.S. industry to compete favorably in the world market for advanced electronics. Materials and processes are discussed in terms of the final properties achievable and systems design compatibility. Weak points in the domestic industrial capability, including technical, industrial philosophy, and political, are identified. Recommendations are presented for actions that could help U.S. industry regain its former leadership position in advanced semiconductor systems production

JTEC Panel report on electronic manufacturing and packaging in Japan

This report summarizes the status of electronic manufacturing and packaging technology in Japan in comparison to that in the United States, and its impact on competition in electronic manufacturing in general. In addition to electronic manufacturing technologies, the report covers technology and manufacturing infrastructure, electronics manufacturing and assembly, quality assurance and reliability in the Japanese electronics industry, and successful product realization strategies. The panel found that Japan leads the United States in almost every electronics packaging technology. Japan clearly has achieved a strategic advantage in electronics production and process technologies. Panel members believe that Japanese competitors could be leading U.S. firms by as much as a decade in some electronics process technologies

Deep Space Network information system architecture study

The purpose of this article is to describe an architecture for the Deep Space Network (DSN) information system in the years 2000-2010 and to provide guidelines for its evolution during the 1990s. The study scope is defined to be from the front-end areas at the antennas to the end users (spacecraft teams, principal investigators, archival storage systems, and non-NASA partners). The architectural vision provides guidance for major DSN implementation efforts during the next decade. A strong motivation for the study is an expected dramatic improvement in information-systems technologies, such as the following: computer processing, automation technology (including knowledge-based systems), networking and data transport, software and hardware engineering, and human-interface technology. The proposed Ground Information System has the following major features: unified architecture from the front-end area to the end user; open-systems standards to achieve interoperability; DSN production of level 0 data; delivery of level 0 data from the Deep Space Communications Complex, if desired; dedicated telemetry processors for each receiver; security against unauthorized access and errors; and highly automated monitor and control

Center for Aeronautics and Space Information Sciences

This report summarizes the research done during 1991/92 under the Center for Aeronautics and Space Information Science (CASIS) program. The topics covered are computer architecture, networking, and neural nets

A Low Temperature Co-fired Ceramic (LTCC) Interposer Based Three-Dimensional Stacked Wire Bondless Power Module

The objective of this dissertation research is to develop a low temperature co-fired ceramic (LTCC) interposer-based module-level 3-D wire bondless stacked power module. As part of the dissertation work, the 3-D wire bondless stack is designed, simulated, fabricated and characterized. The 3-D wire bondless stack is realized with two stand-alone power modules in a half-bridge configuration. Each stand-alone power module consists of two 1200 V 25 A silicon insulated-gate bipolar transistor (IGBT) devices in parallel and two 1200 V 20 A Schottky barrier diodes (SBD) in an antiparallel configuration. A novel interconnection scheme with conductive clamps and a spring loaded LTCC interposer is introduced to establish electrical connection between the stand-alone power modules to connect them in series to realize a half-bridge stack. Process development to fabricate the LTCC based 3-D stack is performed. In traditional power modules, wire bonds are used as a top side interconnections that introduce additional parasitic inductance in the current conduction path and prone to failure mechanism under high thermomechanical stresses. The loop inductance of the proposed 3-D half-bridge module exhibits 71% lower parasitic inductance compared to a wire bonded module. The 3-D stack exhibits better switching performance compared to the wire bonded counterpart. The measurement results for the 3-D stack shows 30% decrease in current overshoot at turn-on and 43% voltage overshoot at turn-off compared to the wire bonded module. Through measurements, it has been shown that the conducted noise reduces by 20 dB in the frequency range 20-30 MHz for the 3-D stack compared to the wire bonded counterpart. A simulation methodology using co-simulation techniques using ANSYS EM software tools is developed to predict EMI of a power module. Hardware verification of the proposed simulation methodology is performed to validate the co-simulation technique. The correlation coefficient between the measurement and simulation is found to be 0.73. It is shown that 53% of the variability in the simulation can be explained by the simulated result. Moreover, the simulated and measured amplitudes of the EMI spectrum closely match with each other with some variations due to round-off errors due to the FFT conversion

Performance of the upgraded PreProcessor of the ATLAS Level-1 Calorimeter Trigger

The PreProcessor of the ATLAS Level-1 Calorimeter Trigger prepares the analogue trigger signals sent from the ATLAS calorimeters by digitising, synchronising, and calibrating them to reconstruct transverse energy deposits, which are then used in further processing to identify event features. During the first long shutdown of the LHC from 2013 to 2014, the central components of the PreProcessor, the Multichip Modules, were replaced by upgraded versions that feature modern ADC and FPGA technology to ensure optimal performance in the high pile-up environment of LHC Run 2. This paper describes the features of the newMultichip Modules along with the improvements to the signal processing achieved.ANPCyTYerPhI, ArmeniaAustralian Research CouncilBMWFW, AustriaAustrian Science Fund (FWF)Azerbaijan National Academy of Sciences (ANAS)SSTC, BelarusNational Council for Scientific and Technological Development (CNPq)Fundacao de Amparo a Pesquisa do Estado de Sao Paulo (FAPESP)Natural Sciences and Engineering Research Council of CanadaCanada Foundation for InnovationNational Natural Science Foundation of China (NSFC)Departamento Administrativo de Ciencia, Tecnología e Innovación ColcienciasMinistry of Education, Youth & Sports - Czech Republic Czech Republic GovernmentCzech Republic GovernmentDNRF, DenmarkDanish Natural Science Research CouncilCentre National de la Recherche Scientifique (CNRS)CEA-DRF/IRFU, FranceFederal Ministry of Education & Research (BMBF)Max Planck SocietyGreek Ministry of Development-GSRTRGC and Hong Kong SAR, ChinaIsrael Science FoundationBenoziyo Center, IsraelIstituto Nazionale di Fisica Nucleare (INFN)Ministry of Education, Culture, Sports, Science and Technology, Japan (MEXT)Ministry of Education, Culture, Sports, Science and Technology, Japan (MEXT) Japan Society for the Promotion of ScienceCNRST, MoroccoRCN, NorwayPortuguese Foundation for Science and TechnologyMNE/IFA, RomaniaMES of RussiaMESTD, SerbiaMSSR, SlovakiaSlovenian Research Agency - SloveniaMIZS, SloveniaSpanish GovernmentSRC, SwedenWallenberg Foundation, SwedenSNSF Geneva, SwitzerlandMinistry of Science and Technology, TaiwanMinistry of Energy & Natural Resources - TurkeyScience & Technology Facilities Council (STFC)United States Department of Energy (DOE)National Science Foundation (NSF)BCKDF, CanadaCANARIE, CanadaCRC, CanadaEuropean Research Council (ERC)European Union (EU)French National Research Agency (ANR)German Research Foundation (DFG)Alexander von Humboldt FoundationGreek NSRF, GreeceBSF-NSF, IsraelGerman-Israeli Foundation for Scientific Research and DevelopmentLa Caixa Banking Foundation, SpainCERCA Programme Generalitat de Catalunya, SpainPROMETEO, SpainGenT Programmes Generalitat Valenciana, SpainGoran Gustafssons Stiftelse, SwedenRoyal Society of LondonLeverhulme TrustNRC, CanadaCERNANID, ChileChinese Academy of SciencesMinistry of Science and Technology, ChinaSRNSFG, GeorgiaHGF, GermanyNetherlands Organization for Scientific Research (NWO) Netherlands GovernmentMinistry of Science and Higher Education, PolandNCN, PolandNRCKI, Russia FederationJINRDST/NRF, South AfricaSERI, Geneva, SwitzerlandCantons of Bern and Geneva, SwitzerlandCompute Canada, CanadaHorizon 2020Marie Sklodowska-Curie ActionsEuropean Cooperation in Science and Technology (COST)EU-ESF, Greec