High-Performance Energy-Efficient and Reliable Design of Spin-Transfer Torque Magnetic Memory

In this dissertation new computing paradigms, architectures and design philosophy are proposed and evaluated for adopting the STT-MRAM technology as highly reliable, energy efficient and fast memory. For this purpose, a novel cross-layer framework from the cell-level all the way up to the system- and application-level has been developed. In these framework, the reliability issues are modeled accurately with appropriate fault models at different abstraction levels in order to analyze the overall failure rates of the entire memory and its Mean Time To Failure (MTTF) along with considering the temperature and process variation effects. Design-time, compile-time and run-time solutions have been provided to address the challenges associated with STT-MRAM. The effectiveness of the proposed solutions is demonstrated in extensive experiments that show significant improvements in comparison to state-of-the-art solutions, i.e. lower-power, higher-performance and more reliable STT-MRAM design

Performance Analysis of NAND Flash Memory Solid-State Disks

As their prices decline, their storage capacities increase, and their endurance improves, NAND Flash Solid-State Disks (SSD) provide an increasingly attractive alternative to Hard Disk Drives (HDD) for portable computing systems and PCs. HDDs have been an integral component of computing systems for several decades as long-term, non-volatile storage in memory hierarchy. Today's typical hard disk drive is a highly complex electro-mechanical system which is a result of decades of research, development, and fine-tuned engineering. Compared to HDD, flash memory provides a simpler interface, one without the complexities of mechanical parts. On the other hand, today's typical solid-state disk drive is still a complex storage system with its own peculiarities and system problems. Due to lack of publicly available SSD models, we have developed our NAND flash SSD models and integrated them into DiskSim, which is extensively used in academe in studying storage system architectures. With our flash memory simulator, we model various solid-state disk architectures for a typical portable computing environment, quantify their performance under real user PC workloads and explore potential for further improvements. We find the following: * The real limitation to NAND flash memory performance is not its low per-device bandwidth but its internal core interface. * NAND flash memory media transfer rates do not need to scale up to those of HDDs for good performance. * SSD organizations that exploit concurrency at both the system and device level improve performance significantly. * These system- and device-level concurrency mechanisms are, to a significant degree, orthogonal: that is, the performance increase due to one does not come at the expense of the other, as each exploits a different facet of concurrency exhibited within the PC workload. * SSD performance can be further improved by implementing flash-oriented queuing algorithms, access reordering, and bus ordering algorithms which exploit the flash memory interface and its timing differences between read and write requests

Integration of Non-volatile Memory into Storage Hierarchy

In this dissertation, we present novel approaches for integrating non-volatile memory devices into storage hierarchy of a computer system. There are several types of non- volatile memory devices, such as flash memory, Phase Change Memory (PCM), Spin- transfer torque memory (STT-RAM). These devices have many appealing features for applications; however, they also offer several challenges. This dissertation is focused on how to efficiently integrate these non-volatile memories into existing memory and disk storage systems. This work is composed of two major parts. The first part investigates a main-memory system employing Phase Change Memory instead of traditional DRAM. Compared to DRAM, PCM has higher density and no static power consumption, which are very important factors for building large capacity memory systems. However, PCM has higher write latency and power consumption compared to read operations. Moreover, PCM has limited write endurance. To efficiently integrate PCM into a memory system, we have to solve the challenges brought by its expensive write operations. We propose new replacement policies and cache organizations for the last-level CPU cache, which can effectively reduce the write traffic to the PCM main memory. We evaluated our design with multiple workloads and configurations. The results show that the proposed approaches improve the lifetime and energy consumption of PCM significantly. The second part of the dissertation considers the design of a data/disk storage using non-volatile memories, e.g. flash memory, PCM and nonvolatile DIMMs. We consider multiple design options for utilizing the nonvolatile memories in the storage hierarchy. First, we consider a system that employs nonvolatile memories such as PCM or nonvolatile DIMMs on memory bus along with flash-based SSDs. We propose a hybrid file system, NVMFS, that manages both these devices. NVMFS exploits the nonvolatile memory to improve the characteristics of the write workload at the SSD. We satisfy most small random write requests on the fast nonvolatile DIMM and only do large and optimized writes on SSD. We also group data of similar update patterns together before writing to flash-SSD; as a result, we can effectively reduce the garbage collection overhead. We implemented a prototype of NVMFS in Linux and evaluated its performance through multiple benchmarks. Secondly, we consider the problem of using flash memory as a cache for a disk drive based storage system. Since SSDs are expensive, a few SSDs are designed to serve as a cache for a large number of disk drives. SSD cache space can be used for both read and write requests. In our design, we managed multiple flash-SSD devices directly at the cache layer without the help of RAID software. To ensure data reliability and cache space efficiency, we only duplicated dirty data on flash- SSDs. We also balanced the write endurance of different flash-SSDs. As a result, no single SSD will fail much earlier than the others. Thirdly, when using PCM-like devices only as data storage, it’s possible to exploit memory management hardware resources to improve file system performance. However, in this case, PCM may share critical system resources such as the TLB, page table with DRAM which can potentially impact PCM’s performance. To solve this problem, we proposed to employ superpages to reduce the pressure on memory management resources. As a result, the file system performance is further improved

전자 장치 내 국부적 전계 향상을 위한 나노 구조체

학위논문(박사) -- 서울대학교대학원 : 공과대학 화학생물공학부, 2021.8. 조재영.The goal of this dissertation is to investigate effect of nanostructures for local electric field enhancement in electronic devices and to provide experimental and theoretical bases for their practical use. Resistive random access memory (RRAM) is a data storage device that can be modulated its resistance states by external electrical stimuli. The electric field generated by the applied potential difference between the two electrodes acts as the driving force to switch the resistance states, so controlling the electric field within the device can lead to improved operational performance and reliability of the device. Even though considerable progress has been made through significant efforts to control the electric field within the device, selectively enhancing the electric field in the intended position for stable and uniform resistive switching behavior is still challenging. Engineered metal structures in the RRAM can efficiently manipulate the electric field. As the radius of the metal structures decreases, the charge density increases, generating electric field enhancements in confined region. To minimize the radius of the metal structure and thus to greatly increase the electric field in a local area, we introduced a nanoscale metal structure into the RRAM. First, pyramid-structured metal electrode with a sharp tip was used to achieve a tip-enhanced electric field, and the effect of the enhanced electric field on the resistive switching behaviors of the device was investigated. Based on numerical simulation and experimental results, we confirmed that pyramidal electrode with a tip radius of tens of nanometers can selectively enhance the electric field at the tip. The tip-enhanced electric field can facilitate the thermochemical reaction in transition metal oxide-based RRAMs and efficiency of charge injection and transport in organic-based RRAMs, as well as provide position selectivity during formation of conductive filament. The resulting RRAM exhibited reliable resistive switching behavior and highly improved device performance compared with conventional RRAM with planar electrode. As another approach to enhance the electric field within the resistive switching layer, we prepared spherical nanostructures via self-assembled block copolymer (BCP)/metal compound micelles. BCP and metal precursors were dissolved in aqueous media for use as BCP/metal compound micelles. These micelles were used as complementary resistive switch (CRS) layers of the memory device and the mechanism of CRS behavior was investigated. The spherical metal nanostructures can improve the electric fields, promoting a resistive switching mechanism based on electrochemical metallization. The resulting CRS memory exhibited reliable resistive switching behavior with four distinct threshold voltages in both cycle-to-cycle and cell-to-cell tests. Also, the conduction and resistive switching mechanism are experimentally demonstrated through the the analysis of the current–voltage data plot and detemination of the temperature coefficient of resistance. Overall, we pursued efficient engineering of metal nanostructures capable of manipulating electric fields for improving the operational performance and reliability of memory devices. There is no doubt that the commercialized RRAM will become popular in the near future after overcoming all the challenges of RRAM through continuous interest and research. We believe that these results will not only contribute to the significant advancement of all electronic devices, including RRAM, but will also help promote research activities in the electronic device field.본 논문의 목적은 나노 구조체를 통한 전자 장치 내 국부적 전계 향상 효과를 조사하고, 이의 실제 사용을 위한 실험 및 이론적 기반을 제공하는 것이다. 저항변화메모리 (resistive random access memory) 는 외부 전기 자극에 의해 저항 상태를 변화 시킬 수 있는 데이터 저장 장치이다. 두 전극 사이에 인가된 전위차에 의해 생성된 전기장은 저항 상태를 전환시키는 구동력으로써 작용하므로, 전자 장치 내에서 전기장을 제어하면 장치의 성능과 신뢰성을 향상시킬 수 있다. 장치 내에서 전기장을 제어하려는 많은 노력을 통해 상당한 진전이 있었지만, 안정적이고 균일한 저항 변화 거동을 위해 의도된 위치에서 전기장을 선택적으로 향상시키는 일은 아직 도전적 과제이다. 구조화된 금속을 저항변화메모리에 접목시킴으로써 전기장을 효율적으로 조작할 수 있다. 금속 구조체의 반경이 감소함에 따라 전하 밀도가 증가하여 국부적 영역에서 전기장이 향상된다. 이 논문에서는 금속 구조체의 반경을 최소화하여 국부적으로 전기장을 크게 향상시키기 위해 저항변화메모리에 나노스케일의 금속 구조체를 도입하였다. 첫 번째로, 팁 강화 (tip-enhanced) 전기장 효과를 달성하기 위해 날카로운 팁을 가지는 피라미드 금속 구조체를 전극으로 사용하였으며, 강화된 전기장이 소자의 저항 변화 거동에 미치는 영향을 조사하였다. 유한요소모델링과 실험결과를 바탕으로, 수십 나노 미터의 팁 반경을 가지는 피라미드 구조체 전극이 팁 부근에서 전기장을 국소적으로 향상시킬 수 있음을 확인하였다. 팁 강화 전기장은 전이 금속 산화물-기반 저항변화메모리에서 열화학 (thermochemical) 반응을 촉진시키고 유기-기반 저항변화메모리에서 전하 주입 (charge injection) 및 수송 (transport) 효율성을 향상시킬 뿐 아니라, 선택적인 위치에서만 전도성 필라멘트 (conductive filament)를 형성시킬 수 있었다. 그 결과 피라미드 구조체 저항변화메모리는 종래의 평판 구조체 저항변화메모리에 비해 안정적인 저항 변화 거동과 향상된 장치 성능을 보여주었다. 저항 변화 층 내의 전기장을 향상시키기 위한 또 다른 접근법으로, 자기조립 (self-assembled)된 블록공중합체 (block copolymer)/금속 복합체 미셀 (micelle)을 이용하여 구형의 나노구조체를 소자의 중간층으로 도입하였다. 블록공중합체 및 금속전구체를 복합체 미셀로 사용하기 위해 선택적 용매에 용해시켰다. 해당 미셀을 메모리 소자의 상보적 저항 변화 (complementary resistive switch) 층으로 사용하였으며, 상보적 저항 변화 거동의 메커니즘을 조사하였다. 구형의 금속 나노구조체는 전기장을 향상시켜 전기화학적 금속화 (electrochemical metallization)에 기반한 저항 변화 메커니즘을 촉진시킬 수 있었다. 그 결과 상보적 저항 변화 메모리는 사이클 및 셀간 반복 시험 모두에서 4개의 임계 전압으로 안정적인 저항 변화 동작을 나타내었다. 또한 전류-전압 자료 플롯 (plot) 분석과 저항의 온도 계수 결정을 통해 장치의 전도 및 저항 변화 메커니즘을 실험적으로 입증하였다. 전반적으로 본 논문에서는 장치 내 전기장을 증폭시킬 수 있는 금속 나노구조체의 효율적인 엔지니어링을 통해 메모리 장치의 성능과 신뢰성 향상을 추구하였다. 지속적인 관심과 연구를 통해 저항변화메모리의 모든 과제를 극복한 후, 상용화된 저항변화메모리가 가까운 미래에 대중화될 것임을 믿어 의심치 않는다. 우리는 이 결과가 저항변화메모리를 포함한 모든 전자 장치의 획기적인 발전에 기여할 뿐만 아니라 전자 장치 분야의 연구 활동을 촉진하는 데에도 도움이 될 것이라고 믿는다.Chapter 1. Introduction 1 1.1. Background 1 1.1.1. Necessity of new memory devices 1 1.1.2. Resistive random access memory 2 1.2. Motivation 4 1.3. Dissertation Overview 6 1.4. References 9 Chapter 2. Tip-Enhanced Electric Field-Driven Efficient Charge Injection and Transport in Organic Material-Based Resistive Memories 19 2.1. Introduction 21 2.2. Experimental 24 2.3. Results and Discussion 27 2.4. Conclusions 37 2.5. References 38 Chapter 3. Facilitation of the Thermochemical Mechanism in NiO-Based Resistive Switching Memories via Tip-Enhanced Electric Fields 52 3.1. Introduction 54 3.2. Experimental 57 3.3. Results and Discussion 60 3.4. Conclusions 66 3.5. References 67 Chapter 4. Facile Achievement of Complementary Resistive Switching Behaviors via Self-Assembled Block Copolymer Micelles 82 4.1. Introduction 83 4.2. Experimental 86 4.3. Results and Discussion 89 4.4. Conclusions 96 4.5. References 97 Chapter 5. Conclusion 109 Abstract in Korean 112박

Efficient Methods for Unsupervised Learning of Probabilistic Models

In this thesis I develop a variety of techniques to train, evaluate, and sample from intractable and high dimensional probabilistic models. Abstract exceeds arXiv space limitations -- see PDF

Vector support for multicore processors with major emphasis on configurable multiprocessors

It recently became increasingly difficult to build higher speed uniprocessor chips because of performance degradation and high power consumption. The quadratically increasing circuit complexity forbade the exploration of more instruction-level parallelism (JLP). To continue raising the performance, processor designers then focused on thread-level parallelism (TLP) to realize a new architecture design paradigm. Multicore processor design is the result of this trend. It has proven quite capable in performance increase and provides new opportunities in power management and system scalability. But current multicore processors do not provide powerful vector architecture support which could yield significant speedups for array operations while maintaining arealpower efficiency. This dissertation proposes and presents the realization of an FPGA-based prototype of a multicore architecture with a shared vector unit (MCwSV). FPGA stands for Filed-Programmable Gate Array. The idea is that rather than improving only scalar or TLP performance, some hardware budget could be used to realize a vector unit to greatly speedup applications abundant in data-level parallelism (DLP). To be realistic, limited by the parallelism in the application itself and by the compiler\u27s vectorizing abilities, most of the general-purpose programs can only be partially vectorized. Thus, for efficient resource usage, one vector unit should be shared by several scalar processors. This approach could also keep the overall budget within acceptable limits. We suggest that this type of vector-unit sharing be established in future multicore chips. The design, implementation and evaluation of an MCwSV system with two scalar processors and a shared vector unit are presented for FPGA prototyping. The MicroBlaze processor, which is a commercial IP (Intellectual Property) core from Xilinx, is used as the scalar processor; in the experiments the vector unit is connected to a pair of MicroBlaze processors through standard bus interfaces. The overall system is organized in a decoupled and multi-banked structure. This organization provides substantial system scalability and better vector performance. For a given area budget, benchmarks from several areas show that the MCwSV system can provide significant performance increase as compared to a multicore system without a vector unit. However, a MCwSV system with two MicroBlazes and a shared vector unit is not always an optimized system configuration for various applications with different percentages of vectorization. On the other hand, the MCwSV framework was designed for easy scalability to potentially incorporate various numbers of scalar/vector units and various function units. Also, the flexibility inherent to FPGAs can aid the task of matching target applications. These benefits can be taken into account to create optimized MCwSV systems for various applications. So the work eventually focused on building an architecture design framework incorporating performance and resource management for application-specific MCwSV (AS-MCwSV) systems. For embedded system design, resource usage, power consumption and execution latency are three metrics to be used in design tradeoffs. The product of these metrics is used here to choose the MCwSV system with the smallest value

The design and analysis of novel integrated phase-change photonic memory and computing devices

The current massive growth in data generation and communication challenges traditional computing and storage paradigms. The integrated silicon photonic platform may alleviate the physical limitations resulting from the use of electrical interconnects and the conventional von Neuman computing architecture, due to its intrinsic energy and bandwidth advantages. This work focuses on the development of the phase-change all-photonic memory (PPCM), a device potentially enabling the transition from the electrical to the optical domain by providing the (previously unavailable) non-volatile all-photonic storage functionality. PPCM devices allow for all-optical encoding of the information on the crystal fraction of a waveguide-implemented phase-change material layer, here Ge2Sb2Te5, which in turn modulates the transmitted signal amplitude. This thesis reports novel developments of the numerical methods necessary to emulate the physics of PPCM device operation and performance characteristics, illustrating solutions enabling the realization of a simulation framework modelling the inherently three-dimensional and self-influencing optical, thermal and phase-switching behaviour of PPCM devices. This thesis also depicts an innovative, fast and cost-effective method to characterise the key optical properties of phase-change materials (upon which the performance of PPCM devices depend), exploiting the reflection pattern of a purposely built layer stack, combined with a smart fit algorithm adapting potential solutions drawn from the scientific literature. The simulation framework developed in the thesis is used to analyse reported PPCM experimental results. Numerous sources of uncertainty are underlined, whose systematic analysis reduced to the peculiar non-linear optical properties of Ge2Sb2Te5. Yet, the data fit process validates both the simulation tool and the remaining physical assumptions, as the model captures the key aspects of the PPCM at high optical intensity, and reliably and accurately predicts its behaviour at low intensity, enabling to investigate its underpinning physical mechanisms. Finally, a novel PPCM memory architecture, exploiting the interaction of a much-reduced Ge2Sb2Te5 volume with a plasmonic resonant nanoantenna, is proposed and numerically investigated. The architecture concept is described and the memory functionality is demonstrated, underlining its potential energy and speed improvement on the conventional device by up to two orders of magnitude.Engineering and Physical Sciences Research Council (EPSRC

Flash Memory Devices

Flash memory devices have represented a breakthrough in storage since their inception in the mid-1980s, and innovation is still ongoing. The peculiarity of such technology is an inherent flexibility in terms of performance and integration density according to the architecture devised for integration. The NOR Flash technology is still the workhorse of many code storage applications in the embedded world, ranging from microcontrollers for automotive environment to IoT smart devices. Their usage is also forecasted to be fundamental in emerging AI edge scenario. On the contrary, when massive data storage is required, NAND Flash memories are necessary to have in a system. You can find NAND Flash in USB sticks, cards, but most of all in Solid-State Drives (SSDs). Since SSDs are extremely demanding in terms of storage capacity, they fueled a new wave of innovation, namely the 3D architecture. Today “3D” means that multiple layers of memory cells are manufactured within the same piece of silicon, easily reaching a terabit capacity. So far, Flash architectures have always been based on "floating gate," where the information is stored by injecting electrons in a piece of polysilicon surrounded by oxide. On the contrary, emerging concepts are based on "charge trap" cells. In summary, flash memory devices represent the largest landscape of storage devices, and we expect more advancements in the coming years. This will require a lot of innovation in process technology, materials, circuit design, flash management algorithms, Error Correction Code and, finally, system co-design for new applications such as AI and security enforcement