Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults

In the relatively young field of fault-tolerant cryptography, the main research effort has focused exclusively on the protection of the data path of cryptographic circuits. To date, however, we have not found any work that aims at protecting the control logic of these circuits against fault attacks, which thus remains the proverbial Achilles’ heel. Motivated by a hypothetical yet realistic fault analysis attack that, in principle, could be mounted against any modular exponentiation engine, even one with appropriate data path protection, we set out to close this remaining gap. In this paper, we present guidelines for the design of multifault-resilient sequential control logic based on standard Error-Detecting Codes (EDCs) with large minimum distance. We introduce a metric that measures the effectiveness of the error detection technique in terms of the effort the attacker has to make in relation to the area overhead spent in implementing the EDC. Our comparison shows that the proposed EDC-based technique provides superior performance when compared against regular N-modular redundancy techniques. Furthermore, our technique scales well and does not affect the critical path delay

Classical simulatability, entanglement breaking, and quantum computation thresholds

We investigate the amount of noise required to turn a universal quantum gate set into one that can be efficiently modelled classically. This question is useful for providing upper bounds on fault tolerant thresholds, and for understanding the nature of the quantum/classical computational transition. We refine some previously known upper bounds using two different strategies. The first one involves the introduction of bi-entangling operations, a class of classically simulatable machines that can generate at most bipartite entanglement. Using this class we show that it is possible to sharpen previously obtained upper bounds in certain cases. As an example, we show that under depolarizing noise on the controlled-not gate, the previously known upper bound of 74% can be sharpened to around 67%. Another interesting consequence is that measurement based schemes cannot work using only 2-qubit non-degenerate projections. In the second strand of the work we utilize the Gottesman-Knill theorem on the classically efficient simulation of Clifford group operations. The bounds attained for the pi/8 gate using this approach can be as low as 15% for general single gate noise, and 30% for dephasing noise.Comment: 12 pages, 3 figures. v2: small typos changed, no change to result

Fault-Tolerant Control of a Flux-switching Permanent Magnet Synchronous Machine

Je jasné, že nejúspěšnější konstrukce zahrnuje postup vícefázového řízení, ve kterém každá fáze může být považována za samostatný modul. Provoz kterékoliv z jednotek musí mít minimální vliv na ostatní, a to tak, že v případě selhání jedné jednotky ostatní mohou být v provozu neovlivněny. Modulární řešení vyžaduje minimální elektrické, magnetické a tepelné ovlivnění mezi fázemi řízení (měniče). Synchronní stroje s pulzním tokem a permanentními magnety se jeví jako atraktivní typ stroje, jejíž přednostmi jsou vysoký kroutící moment, jednoduchá a robustní konstrukce rotoru a skutečnost, že permanentní magnety i cívky jsou umístěny společně na statoru. FS-PMSM jsou poměrně nové typy střídavého stroje stator-permanentní magnet, které představují významné přednosti na rozdíl od konvenčních rotorů - velký kroutící moment, vysoký točivý moment, v podstatě sinusové zpětné EMF křivky, zároveň kompaktní a robustní konstrukce díky umístění magnetů a vinutí kotvy na statoru. Srovnání výsledků mezi FS-PMSM a klasickými motory na povrchu upevněnými PM (SPM) se stejnými parametry ukazuje, že FS-PMSM vykazuje větší vzduchové mezery hustoty toku, vyšší točivý moment na ztráty v mědi, ale také vyšší pulzaci díky reluktančnímu momentu. Pro stroje buzené permanentními magnety se jedná o tradiční rozpor mezi požadavkem na vysoký kroutící moment pod základní rychlostí (oblast konstantního momentu) a provozem nad základní rychlostí (oblast konstantního výkonu), zejména pro aplikace v hybridních vozidlech. Je předložena nová topologie synchronního stroje s permanentními magnety a spínaným tokem odolného proti poruchám, která je schopná provozu během vinutí naprázdno a zkratovaného vinutí i poruchách měniče. Schéma je založeno na dvojitě vinutém motoru napájeném ze dvou oddělených vektorově řízených napěťových zdrojů. Vinutí jsou uspořádána takovým způsobem, aby tvořila dvě nezávislé a oddělené sady. Simulace a experimentální výzkum zpřesní výkon během obou scénářů jak za normálního provozu, tak za poruch včetně zkratových závad a ukáží robustnost pohonu za těchto podmínek. Tato práce byla publikována v deseti konferenčních příspěvcích, dvou časopisech a knižní kapitole, kde byly představeny jak topologie pohonu a aplikovaná řídící schémata, tak analýzy jeho schopnosti odolávat poruchám.It has become clear that the most successful design approach involves a multiple phase drive in which each phase may be regarded as a single-module. The operation of any one module must have minimal impact upon the others, so that in the event of that module failing the others can continue to operate unaffected. The modular approach requires that there should be minimal electrical, magnetic and thermal interaction between phases of the drive. Flux-Switching permanent magnet synchronous machines (FS-PMSM) have recently emerged as an attractive machine type virtue of their high torque densities, simple and robust rotor structure and the fact that permanent magnets and coils are both located on the stator. Flux-switching permanent magnet (FS-PMSM) synchronous machines are a relatively new topology of stator PM brushless machine. They exhibit attractive merits including the large torque capability and high torque (power) density, essentially sinusoidal back-EMF waveforms, as well as having a compact and robust structure due to both the location of magnets and armature windings in the stator instead of the rotor as those in the conventional rotor-PM machines. The comparative results between a FS-PMSM and a traditional surface-mounted PM (SPM) motor having the same specifications reveal that FS-PMSM exhibits larger air-gap flux density, higher torque per copper loss, but also a higher torque ripple due to cogging -torque. However, for solely permanent magnets excited machines, it is a traditional contradiction between the requests of high torque capability under the base-speed (constant torque region) and wide speed operation above the base speed (constant power region) especially for hybrid vehicle applications. A novel fault-tolerant FS-PMSM drive topology is presented, which is able to operate during open- and short-circuit winding and converter faults. The scheme is based on a dual winding motor supplied from two separate vector-controlled voltage-sourced inverter drives. The windings are arranged in a way so as to form two independent and isolated sets. Simulation and experimental work will detail the driver’s performance during both healthy- and faulty- scenarios including short-circuit faults and will show the drive robustness to operate in these conditions. The work has been published in ten conference papers, two journal papers and a book chapter, presenting both the topology of the drive and the applied control schemes, as well as analysing the fault-tolerant capabilities of the drive.

Integrating Scale Out and Fault Tolerance in Stream Processing using Operator State Management

As users of big data applications expect fresh results, we witness a new breed of stream processing systems (SPS) that are designed to scale to large numbers of cloud-hosted machines. Such systems face new challenges: (i) to benefit from the pay-as-you-go model of cloud computing, they must scale out on demand, acquiring additional virtual machines (VMs) and parallelising operators when the workload increases; (ii) failures are common with deployments on hundreds of VMs - systems must be fault-tolerant with fast recovery times, yet low per-machine overheads. An open question is how to achieve these two goals when stream queries include stateful operators, which must be scaled out and recovered without affecting query results. Our key idea is to expose internal operator state explicitly to the SPS through a set of state management primitives. Based on them, we describe an integrated approach for dynamic scale out and recovery of stateful operators. Externalised operator state is checkpointed periodically by the SPS and backed up to upstream VMs. The SPS identifies individual operator bottlenecks and automatically scales them out by allocating new VMs and partitioning the check-pointed state. At any point, failed operators are recovered by restoring checkpointed state on a new VM and replaying unprocessed tuples. We evaluate this approach with the Linear Road Benchmark on the Amazon EC2 cloud platform and show that it can scale automatically to a load factor of L=350 with 50 VMs, while recovering quickly from failures. Copyright © 2013 ACM

Magic-State Functional Units: Mapping and Scheduling Multi-Level Distillation Circuits for Fault-Tolerant Quantum Architectures

Quantum computers have recently made great strides and are on a long-term path towards useful fault-tolerant computation. A dominant overhead in fault-tolerant quantum computation is the production of high-fidelity encoded qubits, called magic states, which enable reliable error-corrected computation. We present the first detailed designs of hardware functional units that implement space-time optimized magic-state factories for surface code error-corrected machines. Interactions among distant qubits require surface code braids (physical pathways on chip) which must be routed. Magic-state factories are circuits comprised of a complex set of braids that is more difficult to route than quantum circuits considered in previous work [1]. This paper explores the impact of scheduling techniques, such as gate reordering and qubit renaming, and we propose two novel mapping techniques: braid repulsion and dipole moment braid rotation. We combine these techniques with graph partitioning and community detection algorithms, and further introduce a stitching algorithm for mapping subgraphs onto a physical machine. Our results show a factor of 5.64 reduction in space-time volume compared to the best-known previous designs for magic-state factories.Comment: 13 pages, 10 figure

Multiphase induction motor drives - a technology status review

The area of multiphase variable-speed motor drives in general and multiphase induction motor drives in particular has experienced a substantial growth since the beginning of this century. Research has been conducted worldwide and numerous interesting developments have been reported in the literature. An attempt is made to provide a detailed overview of the current state-of-the-art in this area. The elaborated aspects include advantages of multiphase induction machines, modelling of multiphase induction machines, basic vector control and direct torque control schemes and PWM control of multiphase voltage source inverters. The authors also provide a detailed survey of the control strategies for five-phase and asymmetrical six-phase induction motor drives, as well as an overview of the approaches to the design of fault tolerant strategies for post-fault drive operation, and a discussion of multiphase multi-motor drives with single inverter supply. Experimental results, collected from various multiphase induction motor drive laboratory rigs, are also included to facilitate the understanding of the drive operatio

Algorithmic Based Fault Tolerance Applied to High Performance Computing

We present a new approach to fault tolerance for High Performance Computing system. Our approach is based on a careful adaptation of the Algorithmic Based Fault Tolerance technique (Huang and Abraham, 1984) to the need of parallel distributed computation. We obtain a strongly scalable mechanism for fault tolerance. We can also detect and correct errors (bit-flip) on the fly of a computation. To assess the viability of our approach, we have developed a fault tolerant matrix-matrix multiplication subroutine and we propose some models to predict its running time. Our parallel fault-tolerant matrix-matrix multiplication scores 1.4 TFLOPS on 484 processors (cluster jacquard.nersc.gov) and returns a correct result while one process failure has happened. This represents 65% of the machine peak efficiency and less than 12% overhead with respect to the fastest failure-free implementation. We predict (and have observed) that, as we increase the processor count, the overhead of the fault tolerance drops significantly