A comprehensive approach to MPSoC security: achieving network-on-chip security : a hierarchical, multi-agent approach

Multiprocessor Systems-on-Chip (MPSoCs) are pervading our lives, acquiring ever increasing relevance in a large number of applications, including even safety-critical ones. MPSoCs, are becoming increasingly complex and heterogeneous; the Networks on Chip (NoC paradigm has been introduced to support scalable on-chip communication, and (in some cases) even with reconfigurability support. The increased complexity as well as the networking approach in turn make security aspects more critical. In this work we propose and implement a hierarchical multi-agent approach providing solutions to secure NoC based MPSoCs at different levels of design. We develop a flexible, scalable and modular structure that integrates protection of different elements in the MPSoC (e.g. memory, processors) from different attack scenarios. Rather than focusing on protection strategies specifically devised for an individual attack or a particular core, this work aims at providing a comprehensive, system-level protection strategy: this constitutes its main methodological contribution. We prove feasibility of the concepts via prototype realization in FPGA technology

An Overview of Parallel Symmetric Cipher of Messages

مقدمة: على الرغم من التطورات الهامة في الاتصالات والتكنولوجيا، فقد أثبتت حماية البيانات نفسها كواحدة من أكبر الاهتمامات. يجب تشفير البيانات من أجل الارتباط بشكل آمن وسريع من خلال نقل البيانات التكنولوجية على شبكة الإنترنت. يمكن تعريف عملية التشفير بانها تحويل النص العادي إلى نص مشفر لا يمكن قراءته أو تغييره بواسطة الأشخاص المؤذيين.            طرق العمل: من أجل الحفاظ على الدرجة المطلوبة من الأمان ، استغرقت كل من عمليات تحليل التشفير وفك التشفير وقتًا طويلاً. ومع ذلك, من أجل تقليل مقدار الوقت المطلوب لإكمال عمليات التشفير وفك التشفير، طبق العديد من الباحثين طريقة التشفير بطريقة موازية. لقد كشف البحث الذي تم إجراؤه حول المشكلة عن العديد من الإجابات المحتملة. استخدم الباحثون التوازي لتحسين إنتاجية خوارزمياتهم، مما سمح لهم بتحقيق مستويات أداء أعلى في خوارزمية التشفير.                             النتائج: أظهرت الأبحاث الحديثة حول تقنيات التشفير المتوازي أن وحدات معالجة الرسومات (GPUs) تعمل بشكل أفضل من الأنظمة الأساسية المتوازية الأخرى عند مقارنة مستويات أداء التشفير.   الاستنتاجات: لإجراء بحث مقارنة حول أهم خوارزميات التشفير المتوازية من حيث فعالية أمن البيانات وطول المفتاح والتكلفة والسرعة، من بين أمور أخرى. تستعرض هذه الورقة العديد من الخوارزميات المتوازية الهامة المستخدمة في تشفير البيانات وفك تشفيرها في جميع التخصصات. ومع ذلك، يجب النظر في معايير أخرى لإظهار مصداقية أي تشفير. تعتبر اختبارات العشوائية مهمة جدًا لاكتشافها وتم تسليط الضوء عليها في هذه الدراسة.                                                              Background: Despite significant developments in communications and technology, data protection has established itself as one of the biggest concerns. The data must be encrypted in order to link securely, quickly through web-based technological data transmission. Transforming plain text into ciphered text that cannot be read or changed by malicious people is the process of encryption. Materials and Methods: In order to maintain the required degree of security, both the cryptanalysis and decryption operations took a significant amount of time. However, in order to cut down on the amount of time required for the encryption and decryption operations to be completed, several researchers implemented the cryptography method in a parallel fashion. The research that has been done on the problem has uncovered several potential answers. Researchers used parallelism to improve the throughput of their algorithms, which allowed them to achieve higher performance levels on the encryption algorithm. Results: Recent research on parallel encryption techniques has shown that graphics processing units (GPUs) perform better than other parallel platforms when comparing their levels of encryption performance. Conclusion: To carry out comparison research on the most significant parallel crypto algorithms in terms of data security efficacy, key length, cost, and speed, among other things. This paper reviews various significant parallel algorithms used for data encryption and decryption in all disciplines. However, other criteria must be considered in order to show the trustworthiness of any encryption. Randomness tests are very important to discover and are highlighted in this study

Transmission gate based dual rail logic for differential power analysis resistant circuits

Cryptographic devices with hardware implementation of the algorithms are increasingly being used in various applications. As a consequence, there is an increased need for security against the attacks on the cryptographic system. Among various attack techniques, side channel attacks pose a significant threat to the hardware implementation. Power analysis attacks are a type of side channel attack where the power leakage from the underlying hardware is used to eavesdrop on the hardware operation. Wave pipelined differential and dynamic logic (WDDL) has been found to be an effective countermeasure to power analysis. This thesis studies the use of transmission gate based WDDL implementation for the differential and dynamic logic. Although WDDL is an effective defense against power analysis, the number of gates needed for the design of a secure implementation is double the number of gates used for non-secure operations. In this thesis we propose transmission gate based structures for implementation of wave pipelined dynamic and differential logic to minimize the overhead of this defense against power analysis attacks. A transmission gate WDDL design methodology is presented, and the design and analysis of a secure multiplier is given. The adder structures are compared in terms of security effectiveness and silicon area overhead for three cases: unsecured logic implementation, standard gate WDDL, and transmission gate WDDL. In simulation, the transmission gate WDDL design is seen to have similar power consumption results compared to the standard gate WDDL; however, the transmission gate based circuit uses 10-50% fewer gates compared to the static WDDL

An Improved Public Unclonable Function Design for Xilinx FPGAs for Hardware Security Applications

In the modern era we are moving towards completely connecting many useful electronic devices to each other through internet. There is a great need for secure electronic devices and systems. A lot of money is being invested in protecting the electronic devices and systems from hacking and other forms of malicious attacks. Physical Unclonable Function (PUF) is a low-cost hardware scheme that provides affordable security for electronic devices and systems. This thesis proposes an improved PUF design for Xilinx FPGAs and evaluates and compares its performance and reliability compared to existing PUF designs. Furthermore, the utility of the proposed PUF was demonstrated by using it for hardware Intellectual Property (IP) core licensing and authentication. Hardware Trojan can be used to provide evaluation copy of IP cores for a limited time. After that it disables the functionality of the IP core. A finite state machine (FSM) based hardware trojan was integrated with a binary divider IP core and evaluated for licensing and authentication applications. The proposed PUF was used in the design of hardware trojan. Obfuscation metric measures the effectiveness of hardware trojan. A moderately good obfuscation level was achieved for our hardware trojan

A Security-aware and LUT-based CAD Flow for the Physical Synthesis of eASICs

Numerous threats are associated with the globalized integrated circuit (IC) supply chain, such as piracy, reverse engineering, overproduction, and malicious logic insertion. Many obfuscation approaches have been proposed to mitigate these threats by preventing an adversary from fully understanding the IC (or parts of it). The use of reconfigurable elements inside an IC is a known obfuscation technique, either as a coarse grain reconfigurable block (i.e., eFPGA) or as a fine grain element (i.e., FPGA-like look-up tables). This paper presents a security-aware CAD flow that is LUT-based yet still compatible with the standard cell based physical synthesis flow. More precisely, our CAD flow explores the FPGA-ASIC design space and produces heavily obfuscated designs where only small portions of the logic resemble an ASIC. Therefore, we term this specialized solution an "embedded ASIC" (eASIC). Nevertheless, even for heavily LUT-dominated designs, our proposed decomposition and pin swapping algorithms allow for performance gains that enable performance levels that only ASICs would otherwise achieve. On the security side, we have developed novel template-based attacks and also applied existing attacks, both oracle-free and oracle-based. Our security analysis revealed that the obfuscation rate for an SHA-256 study case should be at least 45% for withstanding traditional attacks and at least 80% for withstanding template-based attacks. When the 80\% obfuscated SHA-256 design is physically implemented, it achieves a remarkable frequency of 368MHz in a 65nm commercial technology, whereas its FPGA implementation (in a superior technology) achieves only 77MHz

ASSESSING AND IMPROVING THE RELIABILITY AND SECURITY OF CIRCUITS AFFECTED BY NATURAL AND INTENTIONAL FAULTS

The reliability and security vulnerability of modern electronic systems have emerged as concerns due to the increasing natural and intentional interferences. Radiation of high-energy charged particles generated from space environment or packaging materials on the substrate of integrated circuits results in natural faults. As the technology scales down, factors such as critical charge, voltage supply, and frequency change tremendously that increase the sensitivity of integrated circuits to natural faults even for systems operating at sea level. An attacker is able to simulate the impact of natural faults and compromise the circuit or cause denial of service. Therefore, instead of utilizing different approaches to counteract the effect of natural and intentional faults, a unified countermeasure is introduced. The unified countermeasure thwarts the impact of both reliability and security threats without paying the price of more area overhead, power consumption, and required time. This thesis first proposes a systematic analysis method to assess the probability of natural faults propagating the circuit and eventually being latched. The second part of this work focuses on the methods to thwart the impact of intentional faults in cryptosystems. We exploit a power-based side-channel analysis method to analyze the effect of the existing fault detection methods for natural faults on fault attack. Countermeasures for different security threats on cryptosystems are investigated separately. Furthermore, a new micro-architecture is proposed to thwart the combination of fault attacks and side-channel attacks, reducing the fault bypass rate and slowing down the key retrieval speed. The third contribution of this thesis is a unified countermeasure to thwart the impact of both natural faults and attacks. The unified countermeasure utilizes dynamically alternated multiple generator polynomials for the cyclic redundancy check (CRC) codec to resist the reverse engineering attack

Enhancing quantum entropy in vacuum-based quantum random number generator

Information-theoretically provable unique true random numbers, which cannot be correlated or controlled by an attacker, can be generated based on quantum measurement of vacuum state and universal-hashing randomness extraction. Quantum entropy in the measurements decides the quality and security of the random number generator. At the same time, it directly determine the extraction ratio of true randomness from the raw data, in other words, it affects quantum random numbers generating rate obviously. In this work, considering the effects of classical noise, the best way to enhance quantum entropy in the vacuum-based quantum random number generator is explored in the optimum dynamical analog-digital converter (ADC) range scenario. The influence of classical noise excursion, which may be intrinsic to a system or deliberately induced by an eavesdropper, on the quantum entropy is derived. We propose enhancing local oscillator intensity rather than electrical gain for noise-independent amplification of quadrature fluctuation of vacuum state. Abundant quantum entropy is extractable from the raw data even when classical noise excursion is large. Experimentally, an extraction ratio of true randomness of 85.3% is achieved by finite enhancement of the local oscillator power when classical noise excursions of the raw data is obvious.Comment: 12 pages,8 figure

Ono: an open platform for social robotics

In recent times, the focal point of research in robotics has shifted from industrial ro- bots toward robots that interact with humans in an intuitive and safe manner. This evolution has resulted in the subfield of social robotics, which pertains to robots that function in a human environment and that can communicate with humans in an int- uitive way, e.g. with facial expressions. Social robots have the potential to impact many different aspects of our lives, but one particularly promising application is the use of robots in therapy, such as the treatment of children with autism. Unfortunately, many of the existing social robots are neither suited for practical use in therapy nor for large scale studies, mainly because they are expensive, one-of-a-kind robots that are hard to modify to suit a specific need. We created Ono, a social robotics platform, to tackle these issues. Ono is composed entirely from off-the-shelf components and cheap materials, and can be built at a local FabLab at the fraction of the cost of other robots. Ono is also entirely open source and the modular design further encourages modification and reuse of parts of the platform