Rapid Prototyping of Embedded Video Processing Systems in FPGA Devices

Design of video processing circuits requires a variety of tools and knowledge, and it is difficult to find the right combination of tools for an efficient design process, specifically when considering open tools for evaluation or educational purpose. This chapter presents an overview of video processing requirements, programmable devices used for embedded video processing and the components of a video processing chain. We propose a novel design flow for generating customizable intellectual property (IP) cores used in streaming video processing applications. This design flow is based on domain-specific modules in Python language. Examples of generated cores are presented

Viewing mathematics teachers’ professional identity in the Kingdom of Saudi Arabia through the Lens of Social Theory of Learning and Gender Schema Theory

The purpose of the study is to explore the profile of the professional identity of Mathematics teachers in the Kingdom of Saudi Arabia under the influence of Social Theory of Learning and Gender Schema Theory. The descriptive approach is used in this study. The sample size of this study is 600 secondary Mathematics teachers. This study used an adapted version of the questionnaire designed by Albaqi'i (2014) to profile the Mathematics Teachers' Professional Identity (TPI) of the participants. The findings of the study showed that there is no significant difference of Mathematics TPI in gender wise, but there is significant differences of Mathematics TPI based on teaching experiences and qualifications among the Mathematics teachers in Kingdom of Saudi Arabia.The finding of the profile analysis gives some implications to understand how TPI is evolved among Mathematics teachers in the Kingdom of Saudi Arabia through the influences of teaching experience and professional development, which represent by their qualifications. The findings also informed that male and female Mathematics teachers did not perceive their professional identity differently, which suggest that Saudi Arabia culture permit equal participation in building their professional identity

An architecture and technology for Ambient Intelligence Node

The era of separate networks is over. The existing technology leaders are preparing a big change in recreation of environment around us. There are several faces for this change. Names like Ambient Intelligence, Ambient Network, IP Multimedia Subsystem and others were created all over the Globe. Regardless of which name is used the new network will combine three main functional principles---it will be: contextual aware, ubiquitous access and intelligent interfaces unified network. Within this thesis two major aspects are defined. First, the definition of the Ambient Intelligence Environment concept is presented. Secondly the architecture vectors for the technology are named. A short overview of the existing technology is followed by details for the chosen technology---FPGA. The overall specifications are incorporated in the design and demonstration of a basic Ambient Intelligence Node created in the System on the Chip (SoC) FPGA technology

Five-Axis Machine Tool Condition Monitoring Using dSPACE Real-Time System

This paper presents the design, development and SIMULINK implementation of the lumped parameter model of C-axis drive from GEISS five-axis CNC machine tool. The simulated results compare well with the experimental data measured from the actual machine. Also the paper describes the steps for data acquisition using ControlDesk and hardware-in-the-loop implementation of the drive models in dSPACE real-time system. The main components of the HIL system are: the drive model simulation and input – output (I/O) modules for receiving the real controller outputs. The paper explains how the experimental data obtained from the data acquisition process using dSPACE real-time system can be used for the development of machine tool diagnosis and prognosis systems that facilitate the improvement of maintenance activities

Improved Development Cycle for 8-bit FPGA-Based Soft-Macros Targeting Complex Algorithms

Developing complex algorithms on 8-bit processors without proper development tools is challenging. This paper integrates a series of novel techniques to improve the development cycle for 8-bit soft-macros such as Xilinx PicoBlaze. The improvements proposed in this paper reduce development time significantly by eliminating the required resynthesis of the whole design upon HDL source code changes. Additionally, a technique is proposed to increase the maximum supported data memory size for PicoBlaze which facilitates development of complex algorithms. Also, a general verification technique is proposed based on a series of testbenches that perform code verification using comparison method. The proposed testbench scenario integrates “Inter-Processor Communication (IPC), shared memory, and interrupt” concepts that lays out a guideline for FPGA developers to verify their own designs using the proposed method. The proposed development cycle relies on a chip that has Programmable Logic (PL) fabric (to hold the soft processor) alongside of a hardened processor (to be used as algorithm verifier), therefore, a Xilinx Zynq Ultrascale+ MPSoC is chosen which has a hardened ARM processor. The development cycle proposed in this paper targets the PicoBlaze, but it can be easily ported to other FPGA macros such as Lattice Mico8, or any non-Xilinx FPGA macros

Programmable Battery Management System

Lithium batteries provide excellent energy storage capabilities at a relatively high density; however, precautions must be taken with these high energy devices to ensure safe operation. A battery management system (BMS) provides protection by monitoring cell and pack voltage levels and maintaining them in a specific range. They limit the output current and disable the output in extreme conditions. Most devices in the targeted power range (\u3c1000W) do not allow the user to manipulate the values for maximum current, cut-off voltage, or other limits. This project introduces the Programmable BMS (PBMS), which instead allows the user to select these values through a physical interface. The interface displays measurements including pack voltage and output current, and it reports additional characteristics of interest such as the battery’s temperature, state of charge, and cumulative number of charge cycles. This level of access and control permits users to receive the maximum performance and safety from common lithium battery packs

Towards low cost prototyping of mobile opportunistic disconnection tolerant networks and systems

Fast emerging mobile edge computing, mobile clouds, Internet of Things (IoT) and cyber physical systems require many novel realistic real time multi-layer algorithms for a wide range of domains, such as intelligent content provision and processing, smart transport, smart manufacturing systems and mobile end user applications. This paper proposes a low cost open source platform, MODiToNeS, which uses commodity hardware to support prototyping and testing of fully distributed multi-layer complex algorithms over real world (or pseudo real) traces. MODiToNeS platform is generic and comprises multiple interfaces that allow real time topology and mobility control, deployment and analysis of different self-organised and self-adaptive routing algorithms, real time content processing, and real time environment sensing with predictive analytics. Our platform also allows rich interactivity with the user. We show deployment and analysis of two vastly different complex networking systems: fault and disconnection aware smart manufacturing sensor network and cognitive privacy for personal clouds. We show that our platform design can integrate both contexts transparently and organically and allows a wide range of analysis

Inverted Fluorescence Microscope

The Inverted Fluorescence Microscope senior project team at Cal Poly, San Luis Obispo designed, assembled, and tested a proof-of-concept inverted fluorescence microscope for the university’s Microfabrication Laboratory. Administrators of the laboratory wished to use fluorescence for research and experiments involving cell growth and flow visualization on the micro-scale, and did not have the budget to purchase one of the costly commercially available options. The scope of this design challenge was to produce a low-cost inverted fluorescence microscope employing available optical components and additional readily sourced parts to expand the use of fluorescence microscopy accessible to undergraduate students in the Microfabrication Laboratory. This document is an account of the final microscope design as well as the engineering design process, project management procedures, and timeline followed to produce a working design verification prototype. The final product successfully resolved images of microfluidic devices in brightfield mode with automated maneuverability in the X-Y plane. It is equipped with fluorescence capabilities, and will serve as a valuable, low-cost research tool and platform for future student projects

Pre-validation of SoC via hardware and software co-simulation

Abstract. System-on-chips (SoCs) are complex entities consisting of multiple hardware and software components. This complexity presents challenges in their design, verification, and validation. Traditional verification processes often test hardware models in isolation until late in the development cycle. As a result, cooperation between hardware and software development is also limited, slowing down bug detection and fixing. This thesis aims to develop, implement, and evaluate a co-simulation-based pre-validation methodology to address these challenges. The approach allows for the early integration of hardware and software, serving as a natural intermediate step between traditional hardware model verification and full system validation. The co-simulation employs a QEMU CPU emulator linked to a register-transfer level (RTL) hardware model. This setup enables the execution of software components, such as device drivers, on the target instruction set architecture (ISA) alongside cycle-accurate RTL hardware models. The thesis focuses on two primary applications of co-simulation. Firstly, it allows software unit tests to be run in conjunction with hardware models, facilitating early communication between device drivers, low-level software, and hardware components. Secondly, it offers an environment for using software in functional hardware verification. A significant advantage of this approach is the early detection of integration errors. Software unit tests can be executed at the IP block level with actual hardware models, a task previously only possible with costly system-level prototypes. This enables earlier collaboration between software and hardware development teams and smoothens the transition to traditional system-level validation techniques.Järjestelmäpiirin esivalidointi laitteiston ja ohjelmiston yhteissimulaatiolla. Tiivistelmä. Järjestelmäpiirit (SoC) ovat monimutkaisia kokonaisuuksia, jotka koostuvat useista laitteisto- ja ohjelmistokomponenteista. Tämä monimutkaisuus asettaa haasteita niiden suunnittelulle, varmennukselle ja validoinnille. Perinteiset varmennusprosessit testaavat usein laitteistomalleja eristyksissä kehityssyklin loppuvaiheeseen saakka. Tämän myötä myös yhteistyö laitteisto- ja ohjelmistokehityksen välillä on vähäistä, mikä hidastaa virheiden tunnistamista ja korjausta. Tämän diplomityön tavoitteena on kehittää, toteuttaa ja arvioida laitteisto-ohjelmisto-yhteissimulointiin perustuva esivalidointimenetelmä näiden haasteiden ratkaisemiseksi. Menetelmä mahdollistaa laitteiston ja ohjelmiston varhaisen integroinnin, toimien luonnollisena välietappina perinteisen laitteistomallin varmennuksen ja koko järjestelmän validoinnin välillä. Yhteissimulointi käyttää QEMU suoritinemulaattoria, joka on yhdistetty rekisterinsiirtotason (RTL) laitteistomalliin. Tämä mahdollistaa ohjelmistokomponenttien, kuten laiteajureiden, suorittamisen kohdejärjestelmän käskysarja-arkkitehtuurilla (ISA) yhdessä kellosyklitarkkojen RTL laitteistomallien kanssa. Työ keskittyy kahteen yhteissimulaation pääsovellukseen. Ensinnäkin se mahdollistaa ohjelmiston yksikkötestien suorittamisen laitteistomallien kanssa, varmistaen kommunikaation laiteajurien, matalan tason ohjelmiston ja laitteistokomponenttien välillä. Toiseksi se tarjoaa ympäristön ohjelmiston käyttämiseen toiminnallisessa laitteiston varmennuksessa. Merkittävä etu tästä lähestymistavasta on integraatiovirheiden varhainen havaitseminen. Ohjelmiston yksikkötestejä voidaan suorittaa jo IP-lohkon tasolla oikeilla laitteistomalleilla, mikä on aiemmin ollut mahdollista vain kalliilla järjestelmätason prototyypeillä. Tämä mahdollistaa aikaisemman ohjelmisto- ja laitteistokehitystiimien välisen yhteistyön ja helpottaa siirtymistä perinteisiin järjestelmätason validointimenetelmiin