Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch

This paper presents a low-cost, self-recoverable, double-node upset tolerant latch aiming at nourishing the lack of these devices in the state of the art, especially featuring self-recoverability while maintaining a low-cost pro le. Thus, this D-latch may be useful for high reliability and high-performance safety-critical applications as it can detect and recover faults happening during holding time in harsh radiation environments. The proposed D-latch design is based on a low-cost single event double-node upset tolerant latch and a rule-based double-node upset (DNU) tolerant latch which provides it with the self-recoverability against DNU, but paired with a low transistor count and high performance. Simulation waveforms support the achievements and demonstrate that this new D-latch is fully self-recoverable against double-node upset. In addition, the minimum improvement of the delay-power-area product of the proposed rule-based design for the low-cost DNU tolerant self-recoverable latch (RB-LDNUR) is 59%, compared with the latest DNU self-recoverable latch on the literature.Spanish Government MCIN/AEI/10.13039/501100011033/FEDER PID2020-117344RB-I00Regional Government P20_00265 P20_00633 B-RNM-680-UGR2

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%

A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology

Abstract Conventional flip‐flops are more vulnerable to particle strikes in a radiation environment. To overcome this disadvantage, in the literature, many radiation‐hardened flip‐flops (FFs) based on techniques like triple modular redundancy, dual interlocked cell, Quatro and guard‐gated Quatro cell, and so on, are discussed. The flip‐flop realized using radiation hardened by design Quatro cell is named as the improved version of Quatro flip‐flop (IVQFF). Single event upset (SEU) at inverter stages of master/slave and at output are the two drawbacks of IVQFF. This study proposes a guard‐gated Quatro FF (GQFF) using guard‐gated Quatro cell and Muller C‐element. To overcome the SEU at inverter stages of IVQFF, in GQFF, the inverter stages are realized in a parallel fashion. A dual‐input Muller C‐element is connected to the GQFF output stage to mask the SEU and thus maintain the correct output. The proposed GQFF tolerates both single node upset (SNU) and double node upset (DNU). It also achieves low power. To prove the efficacy, GQFF and the existing FFs are implemented in 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology. From the simulation results, it may be noted that the GQFF is 100% immune to SNUs and 50% immune to DNUs

Soft-Error Resilience Framework For Reliable and Energy-Efficient CMOS Logic and Spintronic Memory Architectures

The revolution in chip manufacturing processes spanning five decades has proliferated high performance and energy-efficient nano-electronic devices across all aspects of daily life. In recent years, CMOS technology scaling has realized billions of transistors within large-scale VLSI chips to elevate performance. However, these advancements have also continually augmented the impact of Single-Event Transient (SET) and Single-Event Upset (SEU) occurrences which precipitate a range of Soft-Error (SE) dependability issues. Consequently, soft-error mitigation techniques have become essential to improve systems\u27 reliability. Herein, first, we proposed optimized soft-error resilience designs to improve robustness of sub-micron computing systems. The proposed approaches were developed to deliver energy-efficiency and tolerate double/multiple errors simultaneously while incurring acceptable speed performance degradation compared to the prior work. Secondly, the impact of Process Variation (PV) at the Near-Threshold Voltage (NTV) region on redundancy-based SE-mitigation approaches for High-Performance Computing (HPC) systems was investigated to highlight the approach that can realize favorable attributes, such as reduced critical datapath delay variation and low speed degradation. Finally, recently, spin-based devices have been widely used to design Non-Volatile (NV) elements such as NV latches and flip-flops, which can be leveraged in normally-off computing architectures for Internet-of-Things (IoT) and energy-harvesting-powered applications. Thus, in the last portion of this dissertation, we design and evaluate for soft-error resilience NV-latching circuits that can achieve intriguing features, such as low energy consumption, high computing performance, and superior soft errors tolerance, i.e., concurrently able to tolerate Multiple Node Upset (MNU), to potentially become a mainstream solution for the aerospace and avionic nanoelectronics. Together, these objectives cooperate to increase energy-efficiency and soft errors mitigation resiliency of larger-scale emerging NV latching circuits within iso-energy constraints. In summary, addressing these reliability concerns is paramount to successful deployment of future reliable and energy-efficient CMOS logic and spintronic memory architectures with deeply-scaled devices operating at low-voltages

Radiation Tolerant Electronics, Volume II

Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade.After the success of the first Special Issue on Radiation Tolerant Electronics, the current Special Issue features thirteen articles highlighting recent breakthroughs in radiation tolerant integrated circuit design, fault tolerance in FPGAs, radiation effects in semiconductor materials and advanced IC technologies and modelling of radiation effects

Highly Reliable Quadruple-Node Upset-Tolerant D-Latch

This work was supported in part by the Spanish MCIN/AEI /10.13039/501100011033/ FEDER under Grant PID2020-117344RB-I00, and in part by the Regional Government under Grant P20_00265 and Grant P20_00633.As CMOS technology scaling pushes towards the reduction of the length of transistors, electronic circuits face numerous reliability issues, and in particular nodes of D-latches at nano-scale confront multiple-node upset errors due to their operation in harsh radiative environments. In this manuscript, a new high reliable D-latch which can tolerate quadruple-node upsets is presented. The design is based on a low-cost single event double-upset tolerant (LSEDUT) cell and a clock-gating triple-level soft-error interceptive module (CG-SIM). Due to its LSEDUT base, it can tolerate two upsets, but the combination of two LSEDUTs and the triple-level CG-SIM provides the proposed D-latch with remarkable quadruple-node upsets (QNU) tolerance. Applying LSEDUTs for designing a QNU-tolerant D-latch improves considerably its features; in particular, this approach enhances its reliability against process variations, such as threshold voltage and (W/L) transistor variability, compared to previous QNU-tolerant D-latches and double-node-upset tolerant latches. Furthermore, the proposed D-latch not only tolerates QNUs, but it also features a clear advantage in comparison with the previous clock gating-based quadruple-node-upset-tolerant (QNUTL-CG) D-latch: it can mask single event transients. Speci c gures of merit endorse the gains introduced by the new design: compared with the QNUTL-CG D-latch, the improvements of the maximum standard deviations of the gate delay, induced by threshold voltage and (W/L) transistors variability of the proposed D-latch, are 13.8% and 5.7%, respectively. Also, the proposed D-latch has 23% lesser maximum standard deviation in power consumption, resulting from threshold voltage variability, when compared to the QNUTL-CG D-latch.Spanish MCIN/AEI /10.13039/501100011033/ FEDER under Grant PID2020-117344RB-I00Regional Government under Grant P20_00265 and Grant P20_0063

High-Performance Robust Latches

First, a new high-performance robust latch (referred to as HiPeR latch) is presented that is insensitive to transient faults affecting its internal and output nodes by design, independently of the size of its transistors. Then, a modified version of the HiPeR latch (referred as HiPeR-CG) is proposed that is suitable to be used together with clock gating. Both proposed latches are faster than the latches most recently presented in the literature, while providing better or comparable robustness to transient faults, at comparable or lower costs in terms of area and power, respectively. Therefore, thanks to the good trade-offs in terms of performance, robustness, and cost, our proposed latches are particularly suitable to be adopted on critical paths

INVESTIGATING THE EFFECTS OF SINGLE-EVENT UPSETS IN STATIC AND DYNAMIC REGISTERS

Radiation-induced single-event upsets (SEUs) pose a serious threat to the reliability of registers. The existing SEU analyses for static CMOS registers focus on the circuit-level impact and may underestimate the pertinent SEU information provided through node analysis. This thesis proposes SEU node analysis to evaluate the sensitivity of static registers and apply the obtained node information to improve the robustness of the register through selective node hardening (SNH) technique. Unlike previous hardening techniques such as the Triple Modular Redundancy (TMR) and the Dual Interlocked Cell (DICE) latch, the SNH method does not introduce larger area overhead. Moreover, this thesis also explores the impact of SEUs in dynamic flip-flops, which are appealing for the design of high-performance microprocessors. Previous work either uses the approaches for static flip-flops to evaluate SEU effects in dynamic flip-flops or overlook the SEU injected during the precharge phase. In this thesis, possible SEU sensitive nodes in dynamic flip-flops are re-examined and their window of vulnerability (WOV) is extended. Simulation results for SEU analysis in non-hardened dynamic flip-flops reveal that the last 55.3 % of the precharge time and a 100% evaluation time are affected by SEUs

Cross-Layer Optimization for Power-Efficient and Robust Digital Circuits and Systems

With the increasing digital services demand, performance and power-efficiency become vital requirements for digital circuits and systems. However, the enabling CMOS technology scaling has been facing significant challenges of device uncertainties, such as process, voltage, and temperature variations. To ensure system reliability, worst-case corner assumptions are usually made in each design level. However, the over-pessimistic worst-case margin leads to unnecessary power waste and performance loss as high as 2.2x. Since optimizations are traditionally confined to each specific level, those safe margins can hardly be properly exploited. To tackle the challenge, it is therefore advised in this Ph.D. thesis to perform a cross-layer optimization for digital signal processing circuits and systems, to achieve a global balance of power consumption and output quality. To conclude, the traditional over-pessimistic worst-case approach leads to huge power waste. In contrast, the adaptive voltage scaling approach saves power (25% for the CORDIC application) by providing a just-needed supply voltage. The power saving is maximized (46% for CORDIC) when a more aggressive voltage over-scaling scheme is applied. These sparsely occurred circuit errors produced by aggressive voltage over-scaling are mitigated by higher level error resilient designs. For functions like FFT and CORDIC, smart error mitigation schemes were proposed to enhance reliability (soft-errors and timing-errors, respectively). Applications like Massive MIMO systems are robust against lower level errors, thanks to the intrinsically redundant antennas. This property makes it applicable to embrace digital hardware that trades quality for power savings.Comment: 190 page