Vertical Heterostructure III-V MOSFETs for CMOS, RF and Memory Applications

This thesis focuses mainly on the co-integration of vertical nanowiren-type InAs and p-type GaSb MOSFETs on Si (Paper I & II), whereMOVPE grown vertical InAs-GaSb heterostructure nanowires areused for realizing monolithically integrated and co-processed all-III-V CMOS.Utilizing a bottom-up approach based on MOVPE grown nanowires enablesdesign flexibilities, such as in-situ doping and heterostructure formation,which serves to reduce the amount of mask steps during fabrication. By refiningthe fabrication techniques, using a self-aligned gate-last process, scaled10-20 nm diameters are achieved for balanced drive currents at Ion ∼ 100μA/μm, considering Ioff at 100 nA/μm (VDD = 0.5 V). This is enabledby greatly improved p-type MOSFET performance reaching a maximumtransconductance of 260 μA/μm at VDS = 0.5 V. Lowered power dissipationfor CMOS circuits requires good threshold voltage VT matching of the n- andp-type device, which is also demonstrated for basic inverter circuits. Thevarious effects contributing to VT-shifts are also studied in detail focusing onthe InAs channel devices (with highest transconductance of 2.6 mA/μm), byusing Electron Holography and a novel gate position variation method (PaperV).The advancements in all-III-V CMOS integration spawned individual studiesinto the strengths of the n- and p-type III-V devices, respectively. Traditionallymaterials such as InAs and InGaAs provide excellent electrontransport properties, therefore they are frequently used in devices for highfrequency RF applications. In contrast, the III-V p-type alternatives have beenlacking performance mostly due to the difficult oxidation properties of Sb-based materials. Therefore, a study of the GaSb properties, in a MOSFETchannel, was designed and enabled by new manufacturing techniques, whichallowed gate-length scaling from 40 to 140 nm for p-type Sb-based MOSFETs(Paper III). The new fabrication method allowed for integration of deviceswith symmetrical contacts as compared to previous work which relied on atunnel-contact at the source-side. By modelling based on measured data fieldeffecthole mobility of 70 cm2/Vs was calculated, well in line with previouslyreported studies on GaSb nanowires. The oxidation properties of the GaSbgate-stack was further characterized by XPS, where high intensities of xraysare achieved using a synchrotron source allowed for characterization ofnanowires (Paper VI). Here, in-situ H2-plasma treatment, in parallel with XPSmeasurements, enabled a study of the time-dependence during full removalof GaSb native oxides.The last focus of the thesis was building on the existing strengths of verticalheterostructure III-V n-type (InAs-InGaAs graded channel) devices. Typically,these devices demonstrate high-current densities (gm >3 mS/μm) and excellentmodulation properties (off-state current down to 1 nA/μm). However,minimizing the parasitic capacitances, due to various overlaps originatingfrom a low access-resistance design, has proven difficult. Therefore, newmethods for spacers in both the vertical and planar directions was developedand studied in detail. The new fabrication methods including sidewall spacersachieved gate-drain capacitance CGD levels close to 0.2 fF/μm, which isthe established limit by optimized high-speed devices. The vertical spacertechnology, using SiO2 on the nanowire sidewalls, is further improved inthis thesis which enables new co-integration schemes for memory arrays.Namely, the refined sidewall spacer method is used to realize selective recessetching of the channel and reduced capacitance for large array memoryselector devices (InAs channel) vertically integrated with Resistive RandomAccess Memory (RRAM) memristors. (Paper IV) The fabricated 1-transistor-1-memristor (1T1R) demonstrator cell shows excellent endurance and retentionfor the RRAM by maintaining constant ratio of the high and low resistive state(HRS/LRS) after 106 switching cycles

Investigation into digital circuit design with GaAs/Ga2O3 heterostructure MOSFETs

In this thesis, GaAs heterostructure MOSFETs are investigated as a potential technology for digital circuit design. The devices under investigation are 0.6 μm gate length, enhancement mode, heterostructure MOSFETs, with a high-κ dielectric (Ga2O3), and an InGaAs channel. Historically silicon CMOS technology has been the natural choice for digital circuits, however the realisation of GaAs MOSFET digital circuits could allow full integration of RF, optoelectronic and digital circuits on a single system-on-chip. Additionally, there are potential performance advantages in using GaAs due to it's high electron mobility. For the first time compact models of complimentary GaAs/Ga2O3 MOS are developed to enable an investigation into establishing a digital design methodology for GaAs MOS. Drift-diffusion models are developed and calibrated to measured device data. These models then provide information on the necessary device parameters to build compact models of these devices. BSIM3v3.2 compact models are developed based on this to enable GaAs MOS technology to be investigated using standard circuit design tools. The compact models have been adapted to ensure that they are physically relevant for GaAs devices. This includes some necessary approximations using effective medium theory. Further adjustments, or ratio corrections, are introduced to ensure that the internal physical parameters of BSIM will be correct. The models are compared to similarly-sized silicon devices to investigate the difference in performance between GaAs and silicon MOSFETs. As expected, the GaAs NMOS devices demonstrate improvements in drive current over silicon. However, the GaAs PMOS devices do not offer this advantage due to low hole mobility. Therefore, as a consequence of the high mobility ratio in GaAs, it is important to consider alternative digital design methodologies to CMOS to optimise performance. The performance of benchmark circuits is investigated for this technology in various digital design styles including CMOS, NMOS saturated enhancement load, and NMOS precharge. GaAs digital circuits gain a signifcant advantage in using alternative design styles to CMOS due to the relatively poor performance of the PMOS devices. In using the alternative styles the number of PMOS devices used can be minimised, and it is shown that NMOS precharge offers both speed and power advantages for this technology. The particular GaAs technology investigated does not outperform silicon in terms of speed and power. However, it has allowed a methodology to be established for future device generations, where performance is anticipated to improve signifcantly

A Study on SPICE Modeling of Non-Resonant Plasmonic Terahertz Detector

Department Of Electrical EngineeringThe terahertz (sub-millimeter wave) is the frequency resource, ranging from 100 GHz ~ 10 THz band, located in the middle region of the infrared and millimeter waves in the electromagnetic spectrum. Terahertz waves has unique physical characteristics, which is transparency of radio waves and straightness of light waves, simultaneously. The terahertz wave is applied to the basic science, such as device, spectroscopy, and imaging technology. And also adjust in the applied science, such as biomedical engineering, security, environment, information and communication. Which importance already verified. In the new shape of future market is expected to be formed broadly. For this application, operating in the THz frequency detecting device essential. Recently, Current elements operating in terahertz are present, such as compound semiconductor (???-???HBT, HEMT). But, there are disadvantage to use as a high price. Therefore, research have been made of silicon based THz detector in many research groups. Silicon-based nano-technology utilizes a plasma wave transistor technology. Which is using the space-time change of the channel charge density. That causes plasma wave oscillation in the MOSFET (Metal oxide semiconductor field effect transistor) channel and this effect available MOSET operating terahertz regime beyond MOSFET cut-off frequency. So, PWT (plasma wave transistor) is available terahertz detection and oscillation. For integrated possible post processing circuit development in these of terahertz applications system, silicon based PWT compact model is essential thing. For this compact model for spice simulation beyond cut-off frequency, we consider charge time variance model which is NQS (non-quasi-static) model, not quasi-static model. For NQS model two kinds of model exist, first is RC ladder model. That is seral connect MOSFET get rid of parasitic elements. And these complex circuit making the equivalent circuit model, it called New Elmore model. For post processing circuit simulation, fast simulation speed is essential, RC ladder model has a disadvantage (for simulating each segment). In this thesis we using New Elmore model based on Non-resonant plasmonic THz detector modeling, And verified physical validity of our NQS model using the our TCAD model based on Quasi-plasma 2DEG. And we propose fast and accurate compact modelingope

높은 전류 구동능력을 가지는 SiGe 나노시트 구조의 터널링 전계효과 트랜지스터

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 박병국.The development of very-large-scale integration (VLSI) technology has continuously demanded smaller devices to achieve high integration density for faster computing speed or higher capacity. However, in the recent complementary-metal-oxide-semiconductor (CMOS) technology, simple downsizing the dimension of metal-oxide-semiconductor field-effect transistor (MOSFET) no longer guarantees the boosting performance of IC chips. In particular, static power consumption is not reduced while device size is decreasing because voltage scaling is slowed down at some point. The increased off-current due to short-channel effect (SCE) of MOSFET is a representative cause of the difficulty in voltage scaling. To overcome these fundamental limits of MOSFET, many researchers have been looking for the next generation of FET device over the last ten years. Tunnel field-effect transistor (TFET) has been intensively studied for its steep switching characteristics. Nevertheless, the poor current drivability of TFET is the most serious obstacle to become competitive device for MOSFET. In this thesis, TFET with high current drivability in which above-mentioned problem is significantly solved is proposed. Vertically-stacked SiGe nanosheet channels are used to boost carrier injection and gate control. The fabrication technique to form highly-condensed SiGe nanosheets is introduced. TFET is fabricated with MOSFET with the same structure in the CMOS-compatible process. Both technology-computer-aided-design (TCAD) simulation and experimental results are utilized to support and examine the advantages of proposed TFET. From the perspective of the single device, the improvement in switching characteristics and current drivability are quantitatively and qualitatively analyzed. In addition, the device performance is compared to the benchmark of previously reported TFET and co-fabricated MOSFET. Through those processes, the feasibility of SiGe nanosheet TFET is verified. It is revealed that the proposed SiGe nanosheet TFET has notable steeper switching and low leakage in the low drive voltage as an alternative to conventional MOSFET.초고밀도 집적회로 기술의 발전은 고집적도 달성을 통해 단위 칩의 연산 속도 및 용량 향상에 기여할 소형의 소자를 끊임없이 요구하고 있다. 하지만 최신의 상보형 금속-산화막-반도체 (CMOS) 기술에서 금속-산화막-반도체 전계 효과 트랜지스터 (MOSFET) 의 단순한 소형화는 더 이상 집적회로의 성능 향상을 보장해 주지 못하고 있다. 특히 소자의 크기가 줄어드는 반면 정적 전력 소모량은 전압 스케일링의 둔화로 인해 감소되지 않고 있는 상황이다. MOSFET의 짧은 채널 효과로 인해 증가된 누설 전류가 전압 스케일링의 어려움을 주는 대표적 원인으로 꼽힌다. 이러한 근본적인 MOSFET의 한계를 극복하기 위하여 지난 10여년간 새로운 단계의 전계 효과 트랜지스터 소자들이 연구되고 있다. 그 중 터널 전계 효과 트랜지스터(TFET)은 그 특유의 우수한 전원 특성으로 각광받아 집중적으로 연구되고 있다. 많은 연구에도 불구하고, TFET의 부족한 전류 구동 능력은 MOSFET의 대체재로 자리매김하는 데 가장 큰 문제점이 되고 있다. 본 학위논문에서는 상기된 문제점을 해결할 수 있는 우수한 전류 구동 능력을 가진 TFET이 제안되었다. 반송자 유입과 게이트 컨트롤을 향상시킬 수 있는 수직 적층된 실리콘저마늄(SiGe) 나노시트 채널이 사용되었다. 또한, 제안된 TFET은 CMOS 기반 공정을 활용하여 MOSFET과 함께 제작되었다. 테크놀로지 컴퓨터 지원 설계(TCAD) 시뮬레이션과 실제 측정 결과를 활용하여 제안된 소자의 우수성을 검증하였다. 단위 CMOS 소자의 관점에서, 전원 특성과 전류 구동 능력의 향상을 정량적, 정성적 방법으로 분석하였다. 그리고, 제작된 소자의 성능을 기존 제작 및 보고된 TFET 및 함께 제작된 MOSSFET과 비교하였다. 이러한 과정을 통해, 실리콘저마늄 나노시트 TFET의 활용 가능성이 입증되었다. 제안된 실리콘저마늄 나노시트 소자는 주목할 만한 전원 특성을 가졌고 저전압 구동 환경에서 한층 더 낮은 누설 전류를 가짐으로써 향후 MOSFET을 대체할만한 충분한 가능성을 보여주었다.Chapter 1 Introduction 1 1.1. Power Crisis of Conventional CMOS Technology 1 1.2. Tunnel Field-Effect Transistor (TFET) 6 1.3. Feasibility and Challenges of TFET 9 1.4. Scope of Thesis 11 Chapter 2 Device Characterization 13 2.1. SiGe Nanosheet TFET 13 2.2. Device Concept 15 2.3. Calibration Procedure for TCAD simulation 17 2.4. Device Verification with TCAD simulation 21 Chapter 3 Device Fabrication 31 3.1. Fabrication Process Flow 31 3.2. Key Processes for SiGe Nanosheet TFET 33 3.2.1. Key Process 1 : SiGe Nanosheet Formation 34 3.2.2. Key Process 2 : Source/Drain Implantation 41 3.2.3. Key Process 3 : High-κ/Metal gate Formation 43 Chapter 4 Results and Discussion 53 4.1. Measurement Results 53 4.2. Analysis of Device Characteristics 56 4.2.1. Improved Factors to Performance in SiGe Nanosheet TFET 56 4.2.2. Performance Comparison with SiGe Nanosheet MOSFET 62 4.3. Performance Evaluation through Benchmarks 64 4.4. Optimization Plan for SiGe nanosheet TFET 66 4.4.1. Improvement of Quality of Gate Dielectric 66 4.4.2. Optimization of Doping Junction at Source 67 Chapter 5 Conclusion 71 Bibliography 73 Abstract in Korean 81 List of Publications 83Docto

A Study on SPICE Modeling of Non-Resonant Plasmonic Terahertz Detector

Department Of Electrical EngineeringThe terahertz (sub-millimeter wave) is the frequency resource, ranging from 100 GHz ~ 10 THz band, located in the middle region of the infrared and millimeter waves in the electromagnetic spectrum. Terahertz waves has unique physical characteristics, which is transparency of radio waves and straightness of light waves, simultaneously. The terahertz wave is applied to the basic science, such as device, spectroscopy, and imaging technology. And also adjust in the applied science, such as biomedical engineering, security, environment, information and communication. Which importance already verified. In the new shape of future market is expected to be formed broadly. For this application, operating in the THz frequency detecting device essential. Recently, Current elements operating in terahertz are present, such as compound semiconductor (???-???HBT, HEMT). But, there are disadvantage to use as a high price. Therefore, research have been made of silicon based THz detector in many research groups. Silicon-based nano-technology utilizes a plasma wave transistor technology. Which is using the space-time change of the channel charge density. That causes plasma wave oscillation in the MOSFET (Metal oxide semiconductor field effect transistor) channel and this effect available MOSET operating terahertz regime beyond MOSFET cut-off frequency. So, PWT (plasma wave transistor) is available terahertz detection and oscillation. For integrated possible post processing circuit development in these of terahertz applications system, silicon based PWT compact model is essential thing. For this compact model for spice simulation beyond cut-off frequency, we consider charge time variance model which is NQS (non-quasi-static) model, not quasi-static model. For NQS model two kinds of model exist, first is RC ladder model. That is seral connect MOSFET get rid of parasitic elements. And these complex circuit making the equivalent circuit model, it called New Elmore model. For post processing circuit simulation, fast simulation speed is essential, RC ladder model has a disadvantage (for simulating each segment). In this thesis we using New Elmore model based on Non-resonant plasmonic THz detector modeling, And verified physical validity of our NQS model using the our TCAD model based on Quasi-plasma 2DEG. And we propose fast and accurate compact modelingope

Dual material gate field effect transistor (DMG-FET)

Improving performance and suppressing short channel effects are two of the most important issues in present field effect transistors development. Hence, high performance and long channel like behaviors are essential requirements for short channel FETs. This dissertation focuses on new ways to achieve these significant goals. A new field effect transistor - dual material gate FET (DMG-FET) - is presented for the first time. The unique feature of the DMG-FET is its gate which consists of two laterally contacting gate materials with different work functions. This novel gate structure takes advantage of material work function difference in such a way that charge carriers are accelerated more rapidly in the channel and the channel potential near the source is screened from the drain bias after saturation. Using HFET as a vehicle, it is shown that the drive current and transconductance in DMG-FET are therefore substantially enhanced as compared to conventional FET. Moreover, it is observed that the short channel effects such as channel length modulation, DIBL and hot-carrier effect are significantly suppressed. Numerical simulations are employed to investigate the new device structure and related phenomenon. A simple and practical DMG-HFET fabrication process has been developed. The proposed DMG-HFET is thus realized for the first time. Experimental results exhibit improved characteristics as the simulation results predicted

Gated multi-cycle integration (GMCI) for focal plane array (FPA) applications

In this thesis, the model and the theory of gated multi-cycle integration (GMCI) were first developed specifically for focal plane array dealing with repetitive or modulated image. The operational modes of GMCI include gated integration (GI), phase sensitive integration (PSI), multi-point summation, multi-point subtraction, multi-sample averaging and some of their combinations. Thus, the analytic theory of GMCI somehow unifies the theories of gated integration, phase sensitive detection, multiple summation and average. PSI works with background and/or dark current subtraction. As a result, the storage well of a pixel is mainly used for signal integration even if there exists a strong background. Thus, the signal-to-noise ratio, the dynamic range, the sensitivity of the detection and the noise equivalent temperature are greatly improved. For a storage well of 106 electrons, the sensitivity of the FPA operated at PSI mode could be improved by 3 orders. In addition, the transmission windows of PSI peak at odd harmonics of the modulation frequency, and therefore, the detector\u27s IN and other low frequency noise can be attenuated. A switched capacitor integrator was designed and fabricated with HP-0.5gm CMOS processing to demonstrate the feasibility of GMCI. The primary experimental results showed that the minimum detectable signal could be 5 orders less than the background, which is impossible for the conventional readout methods employed by current staring FPAs. The fixed patterns associated with switching charge injection, feedthrough, offset voltage of operational amplifier were addressed and suppressed by taking the differentia of two sampled voltages that correspond to signal integrations with 180° phase difference while keeping the same fixed pattern. GMCI, operated at PSI with multiple averages, is expected to become a powerful method in dealing with repetitive weak image swamped by strong background

InAs Nanowire Devices and Circuits

Since the introduction of the transistor and the integrated circuit, the semiconductor industry has developed at a remarkable pace. By continuously fabricating smaller and faster transistors, it has been possible to maintain an exponential increase in performance, a phenomenon famously described by Moore’s Law. Today, billions of transistors are integrated on a single chip and the size of a transistor is on the scale of tens of nanometres. Until recently, the improvements in performance and integration density have been mostly driven by scaling down the transistor size. However, as the length scale is rapidly approaching that of only a few atoms, this scaling paradigm may not continue forever. Instead, the research community, as well as the industry, is investigating alternative structures and materials in order to further increase the performance. One emerging technology for use in future electronic circuits is transistors based on nanowires. The nanowire transistor structure investigated in this work combines a number of key technologies to achieve a higher performance than traditional Si-based transistors. Epitaxially grown nanowires are naturally oriented in the vertical direction, which means that the devices may be fabricated from the bottom and up. This three-dimensional structure allows a higher integration density and enables the gate to completely surround the channel in a gate-all-around configuration. Combined with a high-k dielectric, this results in an excellent electrostatic gate control. Furthermore, nanowires have the unique ability to combine semiconductor materials with significantly different lattice constants. By introducing InAs as a channel material, a much higher electron mobility than for Si is achieved. In this work, simulations of nanowire-based devices are performed and the ultimate performance is predicted. A nanowire transistor architecture with a realistic footprint is proposed and a roadmap is established for the scaling of the device structure, based on a set of technology nodes. Benchmarking is performed against competing technologies, both from a device and circuit perspective. The physical properties of nanowire transistors, and the corresponding capacitor structure, are investigated by band-structure simulations. Based on these simulations, a ballistic transport model is used to derive the intrinsic transistor characteristics. This is combined with an extensive evaluation and optimization of the parasitic elements in the transistor structure for each technology node. It is demonstrated that an optimized nanowire transistor has the potential to operate at terahertz frequencies, while maintaining a low power consumption. A high quality factor and extremely high integration density is predicted for the nanowire capacitor structure. It is concluded that InAs nanowire devices show great potential for use in future electronic circuits, both in digital and analogue applications

Study On IN0.53GA0.47AS MOS Devices with Plasma-Ph3/N2 Treatment and Device Structure Optimization

Ph.DDOCTOR OF PHILOSOPH

Study of High-k Dielectrics and their Interfaces on Semiconductors for Device Applications

This thesis has focused on two emerging applications of high-k dielectrics in Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and in Metal-InsulatorSemiconductor High Electron Mobility Transistors (MIS-HEMTs). The key aim has been to propose the best routes for passivation of semiconductor/high-k oxide interfaces by investigating the band alignments and interface properties of several oxides, such as Tm2O3, Ta2O5, ZrO2, Al2O3 and MgO, deposited on different semiconductors: Si, Ge, GaN, InGaAs and InGaSb. The electrical characterisation of fabricated MIS capacitor and (MIS)-HEMT devices have also been performed. Thulium silicate (TmSiO) has been identified as a promising candidate for integration as interfacial layer (IL) in HfO2/TiN MOSFETs. The physical properties of Tm2O3/IL/Si interface have been elucidated, where IL (TmSiO) has been formed using different post-deposition annealing (PDA) temperatures, from 550 to 750 °C. It has been found that the best-scaled stack (sub-nm IL) is formed at 550 °C PDA with a graded interface layer and a strong SiOx (Si 3+) component. A large valence band offset (VBO) of 2.8 eV and a large conduction band offset (CBO) of 1.9 eV have been derived for Tm2O3/Si by X-ray photoelectron spectroscopy (XPS) and variable angle spectroscopic ellipsometry. Further increase of device performance can be achieved by replacing Si with GaN for high frequency, high power and high-temperature operation. In this thesis, several GaN cleaning procedures have been considered: 30% NH4OH, 20% (NH4)2S, and 37% HCl. It has been found that the HCl treatment shows the lowest oxygen contamination and Garich surface, and hence has been used prior sputtering of Ta2O5, Al2O3, ZrO2 and MgO on GaN. The large VBOs of 1.1 eV and 1.2 eV have been derived for Al2O3 and MgO on GaN respectively, using XPS and Kraut’s method; the corresponding CBOs are 2.0 eV and 2.8 eV respectively, taking into account the band gaps of Al2O3 (6.5 eV) and MgO (7.4 eV) determined from XPS O 1s electron energy spectra. The lowest leakage currents were obtained for devices with Al2O3 and MgO, i.e. 5.3 ×10-6 A/cm2 and 3.2 ×10-6 A/cm2 at 1 V, respectively in agreement with high band offsets (> 1 eV). Furthermore, the effect of different surface treatments (HCl, O2 plasma and 1-Octadecanethiol (ODT)) prior to atomic layer deposition of Al2O3 on the GaN/AlGaN/GaN heterostructure has been investigated. The MIS-HEMTs fabricated using the low-cost ODT GaN surface treatment have been found to exhibit superior performance for power switching applications such as a low threshold voltage, VT of -12.3 V, hysteresis of 0.12 V, a small subthreshold voltage slope (SS) of 73 mV/dec, and a low density of interface states, Dit of 3.0 x10^12 cm-2eV-1. A comprehensive novel study of HfO2/InGaAs and Al2O3/InGaSb interfaces have also been conducted for use in III-V based MOSFETs. The addition of the plasma H2/TMA/H2 pre-cleaning has been found to be very effective in recovering etch damage on InGaAs, especially for (110) orientation, and led to the improvement of electrical characteristics. Furthermore, the combination of H2 plasma exposure and forming gas anneal yielded significantly improved metrics for Al2O3/InGaSb over the control HCltreated sample, with the 150 W plasma treatment giving both the highest capacitance and the lowest stretch out