A new bulk-driven input stage design for sub 1-volt CMOS op-amps

This paper presents a new design approach for a rail-to-rail bulk-driven input stage using a standard single-well (n-well in this paper) CMOS technology. This input stage can provide nearly constant transconductance and constant slew rate over the entire input common-mode voltage, operating with a wide supply voltage ranging from sub 1-volt (V/sub T0/+ 3V/sub DSsat/) to the maximum allowed for the CMOS process, as well as preventing latch-up

Performance enhancement in the desing of amplifier and amplifier-less circuits in modern CMOS technologies.

In the context of nowadays CMOS technology downscaling and the increasing demand of high performance electronics by industry and consumers, analog design has become a major challenge. On the one hand, beyond others, amplifiers have traditionally been a key cell for many analog systems whose overall performance strongly depends on those of the amplifier. Consequently, still today, achieving high performance amplifiers is essential. On the other hand, due to the increasing difficulty in achieving high performance amplifiers in downscaled modern technologies, a different research line that replaces the amplifier by other more easily achievable cells appears: the so called amplifier-less techniques. This thesis explores and contributes to both philosophies. Specifically, a lowvoltage differential input pair is proposed, with which three multistage amplifiers in the state of art are designed, analysed and tested. Moreover, a structure for the implementation of differential switched capacitor circuits, specially suitable for comparator-based circuits, that features lower distortion and less noise than the classical differential structures is proposed, an, as a proof of concept, implemented in a ΔΣ modulator

Bulk-driven flipped voltage follower

A voltage buffer so-called the bulk-driven flipped voltage follower is presented. This proposal is based on the flipped voltage follower (FVF) technique, but a bulk-driven MOSFET with the replica-biased scheme is utilized for the input device to eliminate the DC level shift. The proposed buffer has been designed and simulated with a 0.35 mum CMOS technology. The input current and capacitance of our proposal are 1.5 pA and 9.3 fF respectively, and with 0.8 V peak-to-peak 500 kHz input, the total harmonic distortion is 0.5% for a 10 pF load. This circuit can operate from a single 1.2 V power supply and consumes only 2.5 muA

Achieving rail-to-rail input operation using level-shift multiplexing technique for all CMOS op-amps

This paper presents a new design approach which can convert any CMOS operational amplifiers to have rail-to-rail common-mode input capability by utilizing few additional hardware elements. The proposed circuit can operate over a wide range of supply voltages from 1-volt to the maximum allowed for the CMOS process, without degrading the ac and dc performances of the amplifier in question over the rail-to-rail operation

Exploiting the bulk-driven approach in CMOS analogue amplifier design

This thesis presents a collection of new novel techniques using the bulk-driven approach, which can lead to performance enhancement in the field of CMOS analogue amplifier design under the very low-supply voltage constraints. In this thesis, three application areas of the bulk-driven approach are focused – at the input-stage of differential pairs, at the source followers, and at the cascode devices. For the input stage of differential pairs, this thesis proposes two new novel circuit design techniques. One of them utilises the concept of the replica-biased scheme in order to solve the non-linearity and latch-up issues, which are the potential problems that come along with the bulk-driven approach. The other proposed circuit design technique utilises the flipped voltage scheme and the Quasi-Floating Gate technique in order to achieve low-power high-speed performances, and furthermore the reversed-biased diode concept to overcome the issue of degraded input impedance characteristics that come along with the bulk-driven approach. Applying the bulk-driven approach in source followers is a new type of circuit blocks in CMOS analogue field, in which to the author’s best knowledge has not been proposed at any literatures in the past. This thesis presents the bulk-driven version of the flipped voltage followers and super source followers, which can lead to eliminating the DC level shift. Furthermore, a technique for programming the DC level shift less than the threshold voltage of a MOSFET, which cannot be achieved by conventional types of source followers, is presented. The effectiveness of the cascode device using the bulk-driven approach is validated by implementing it in a complete schematics design of a fully differential bulk-driven operational transcoductance amplifier (OTA). This proposal leads to solving the lowtranconductance problem of a bulk-driven differential pair, and in effect the open loop gain of the OTA exceeds 60dB using a 0.35μm CMOS technology. The final part of this thesis provides the study result of the input capacitance of a bulk-driven buffer. To verify the use of the BSIM3 MOSFET model in the simulation for predicting the input capacitance, the measurement data of the fabricated device are compared with the postlayout simulation results

Low Voltage Low Power Analogue Circuits Design

Disertační práce je zaměřena na výzkum nejběžnějších metod, které se využívají při návrhu analogových obvodů s využití nízkonapěťových (LV) a nízkopříkonových (LP) struktur. Tyto LV LP obvody mohou být vytvořeny díky vyspělým technologiím nebo také využitím pokročilých technik návrhu. Disertační práce se zabývá právě pokročilými technikami návrhu, především pak nekonvenčními. Mezi tyto techniky patří využití prvků s řízeným substrátem (bulk-driven - BD), s plovoucím hradlem (floating-gate - FG), s kvazi plovoucím hradlem (quasi-floating-gate - QFG), s řízeným substrátem s plovoucím hradlem (bulk-driven floating-gate - BD-FG) a s řízeným substrátem s kvazi plovoucím hradlem (quasi-floating-gate - BD-QFG). Práce je také orientována na možné způsoby implementace známých a moderních aktivních prvků pracujících v napěťovém, proudovém nebo mix-módu. Mezi tyto prvky lze začlenit zesilovače typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za účelem potvrzení funkčnosti a chování výše zmíněných struktur a prvků byly vytvořeny příklady aplikací, které simulují usměrňovací a induktanční vlastnosti diody, dále pak filtry dolní propusti, pásmové propusti a také univerzální filtry. Všechny aktivní prvky a příklady aplikací byly ověřeny pomocí PSpice simulací s využitím parametrů technologie 0,18 m TSMC CMOS. Pro ilustraci přesného a účinného chování struktur je v disertační práci zahrnuto velké množství simulačních výsledků.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the non–conventional ones which are bulk–driven (BD), floating–gate (FG), quasi–floating–gate (QFG), bulk–driven floating–gate (BD–FG) and bulk–driven quasi–floating–gate (BD–QFG) techniques. The thesis also looks at ways of implementing structures of well–known and modern active elements operating in voltage–, current–, and mixed–mode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fully–differential second generation current conveyor (FB–CCII), fully–balanced differential difference amplifier (FB–DDA), voltage differencing transconductance amplifier (VDTA), current–controlled current differencing buffered amplifier (CC–CDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diode–less rectifier and inductance simulations, as well as low–pass, band–pass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.

Exploiting the bulk-driven approach in CMOS analogue amplifier design

This thesis presents a collection of new novel techniques using the bulk-driven approach, which can lead to performance enhancement in the field of CMOS analogue amplifier design under the very low-supply voltage constraints. In this thesis, three application areas of the bulk-driven approach are focused – at the input-stage of differential pairs, at the source followers, and at the cascode devices. For the input stage of differential pairs, this thesis proposes two new novel circuit design techniques. One of them utilises the concept of the replica-biased scheme in order to solve the non-linearity and latch-up issues, which are the potential problems that come along with the bulk-driven approach. The other proposed circuit design technique utilises the flipped voltage scheme and the Quasi-Floating Gate technique in order to achieve low-power high-speed performances, and furthermore the reversed-biased diode concept to overcome the issue of degraded input impedance characteristics that come along with the bulk-driven approach. Applying the bulk-driven approach in source followers is a new type of circuit blocks in CMOS analogue field, in which to the author’s best knowledge has not been proposed at any literatures in the past. This thesis presents the bulk-driven version of the flipped voltage followers and super source followers, which can lead to eliminating the DC level shift. Furthermore, a technique for programming the DC level shift less than the threshold voltage of a MOSFET, which cannot be achieved by conventional types of source followers, is presented. The effectiveness of the cascode device using the bulk-driven approach is validated by implementing it in a complete schematics design of a fully differential bulk-driven operational transcoductance amplifier (OTA). This proposal leads to solving the lowtranconductance problem of a bulk-driven differential pair, and in effect the open loop gain of the OTA exceeds 60dB using a 0.35μm CMOS technology. The final part of this thesis provides the study result of the input capacitance of a bulk-driven buffer. To verify the use of the BSIM3 MOSFET model in the simulation for predicting the input capacitance, the measurement data of the fabricated device are compared with the postlayout simulation results

Digital-based analog processing in nanoscale CMOS ICs for IoT applications

The Internet-of-Things (IoT) concept has been opening up a variety of applications, such as urban and environmental monitoring, smart health, surveillance, and home automation. Most of these IoT applications require more and more power/area efficient Complemen tary Metal–Oxide–Semiconductor (CMOS) systems and faster prototypes (lower time-to market), demanding special modifications in the current IoT design system bottleneck: the analog/RF interfaces. Specially after the 2000s, it is evident that there have been significant improvements in CMOS digital circuits when compared to analog building blocks. Digital circuits have been taking advantage of CMOS technology scaling in terms of speed, power consump tion, and cost, while the techniques running behind the analog signal processing are still lagging. To decrease this historical gap, there has been an increasing trend in finding alternative IC design strategies to implement typical analog functions exploiting Digital in-Concept Design Methodologies (DCDM). This idea of re-thinking analog functions in digital terms has shown that Analog ICs blocks can also avail of the feature-size shrinking and energy efficiency of new technologies. This thesis deals with the development of DCDM, demonstrating its compatibility for Ultra-Low-Voltage (ULV) and Power (ULP) IoT applications. This work proves this state ment through the proposing of new digital-based analog blocks, such as an Operational Transconductance Amplifiers (OTAs) and an ac-coupled Bio-signal Amplifier (BioAmp). As an initial contribution, for the first time, a silicon demonstration of an embryonic Digital-Based OTA (DB-OTA) published in 2013 is exhibited. The fabricated DB-OTA test chip occupies a compact area of 1,426 µm2 , operating at supply voltages (VDD) down to 300 mV, consuming only 590 pW while driving a capacitive load of 80pF. With a Total Harmonic Distortion (THD) lower than 5% for a 100mV input signal swing, its measured small-signal figure of merit (FOMS) and large-signal figure of merit (FOML) are 2,101 V −1 and 1,070, respectively. To the best of this thesis author’s knowledge, this measured power is the lowest reported to date in OTA literature, and its figures of merit are the best in sub-500mV OTAs reported to date. As the second step, mainly due to the robustness limitation of previous DB-OTA, a novel calibration-free digital-based topology is proposed, named here as Digital OTA (DIG OTA). A 180-nm DIGOTA test chip is also developed exhibiting an area below the 1000 µm2 wall, 2.4nW power under 150pF load, and a minimum VDD of 0.25 V. The proposed DIGOTA is more digital-like compared with DB-OTA since no pseudo-resistor is needed. As the last contribution, the previously proposed DIGOTA is then used as a building block to demonstrate the operation principle of power-efficient ULV and ultra-low area (ULA) fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA) such as extreme low area Body Dust. Measured results in 180nm CMOS confirm that the proposed BioDIGOTA can work with a supply voltage down to 400 mV, consuming only 95 nW. The BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art while keeping reasonable system performance, such as 7.6 Noise Efficiency Factor (NEF) with 1.25 µVRMS input-referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of the common-mode rejection ratio (CMRR) and 55 dB of power supply rejection ratio (PSRR). After reviewing the current DCDM trend and all proposed silicon demonstrations, the thesis concludes that, despite the current analog design strategies involved during the analog block development