Frequency-domain transient analysis of multitime partial differential equation systems

Multitime partial differential equations (MPDEs) provide an efficient method to simulate circuits with widely separated rates of inputs. This paper proposes a fast and accurate frequency-domain multitime transient analysis method for MPDE systems, which fills in the gap for the lack of general frequency-domain solver for MPDE systems. A block-pulse function-based multidimensional inverse Laplace transform strategy is adopted. The method can be applied to discrete input systems. Numerical examples then confirm its superior accuracy, under similar efficiency, over time-domain solvers. © 2011 IEEE.published_or_final_versionThe 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC), Hong Kong, 3-5 October 2011. In IFIP International Conference on Very Large Scale Integration Proceedings, 2011, p. 160-16

Exploiting Device Mismatch in Neuromorphic VLSI Systems to Implement Axonal Delays

Sheik S, Chicca E, Indiveri G. Exploiting Device Mismatch in Neuromorphic VLSI Systems to Implement Axonal Delays. Presented at the International Joint Conference on Neural Networks (IJCNN), Brisbane, Australia.Axonal delays are used in neural computation to implement faithful models of biological neural systems, and in spiking neural networks models to solve computationally demanding tasks. While there is an increasing number of software simulations of spiking neural networks that make use of axonal delays, only a small fraction of currently existing hardware neuromorphic systems supports them. In this paper we demonstrate a strategy to implement temporal delays in hardware spiking neural networks distributed across multiple Very Large Scale Integration (VLSI) chips. This is achieved by exploiting the inherent device mismatch present in the analog circuits that implement silicon neurons and synapses inside the chips, and the digital communication infrastructure used to configure the network topology and transmit the spikes across chips. We present an example of a recurrent VLSI spiking neural network that employs axonal delays and demonstrate how the proposed strategy efficiently implements them in hardware

Hough Transform recursive evaluation using Distributed Arithmetic

Paper submitted to the IFIP International Conference on Very Large Scale Integration (VLSI-SOC), Darmstadt, Germany, 2003.The Hough Transform (HT) is a useful technique in image segmentation, concretely for geometrical primitive detection. A Convolution-Based Recursive Method (CBRM) is presented for generic function evaluation. In this approach, calculations are carried out by a unique parametric formula which provides all function points by successive iteration. The case of combined trigonometric functions involved in the calculation of the HT is analyzed under this scope. An architecture for reconfigurable FPGA-based hardware, using Distributed Arithmetic (DA) implements the design. It provides memory and hardware resource saving as well as speed improvements according to the experiments carried out with the HT

NASA SERC 1990 Symposium on VLSI Design

This document contains papers presented at the first annual NASA Symposium on VLSI Design. NASA's involvement in this event demonstrates a need for research and development in high performance computing. High performance computing addresses problems faced by the scientific and industrial communities. High performance computing is needed in: (1) real-time manipulation of large data sets; (2) advanced systems control of spacecraft; (3) digital data transmission, error correction, and image compression; and (4) expert system control of spacecraft. Clearly, a valuable technology in meeting these needs is Very Large Scale Integration (VLSI). This conference addresses the following issues in VLSI design: (1) system architectures; (2) electronics; (3) algorithms; and (4) CAD tools

Grade de Hanan din?mica

WithMoore?slaw,theconstructionoflarge-scalecomponentsusingintegratedcircuits, ie a very-large-scale integration (VLSI) becomes increasingly complex, for this are used tools that seek to build models for a VLSI. Therefore, the proposed work is the implementation of a dynamicHanangridwithlessthan O(n2) complexityfortoolsthatusetheRegenerinearSteiner Minimum Tree (RSMT) to search for circuit integration. In addition to the implementation of the dynamic Hanan grid, an application using minimal paths and a bibliographical review of its operation. The tool is validated by test cases provided by the International Conference On Computer Aided Design (ICCAD) 2017.Com a lei de Moore a constru??o de componentes de larga escala utilizando-se de circuitos integrados, ou seja, uma Very-large-scale integration (VLSI) se torna cada vez mais complexa, para isto s?o utilizadas ferramentas que buscam construir modelos para uma VLSI. Com isto, a proposta deste trabalho ? a implementa??o de uma grade de Hanan din?mica com complexidade de espa?o inferior a O(n2) em ferramentas que se utilizem da Rectilinear Steiner Minimum Tree (RSMT) que buscam a integra??o de circuitos. Tendo como contribui??o, al?m da implementa??o da grade de Hanan din?mica, uma aplica??o utilizando caminhos min?mos e uma revis?o bibliogr??ca do funcionamento da mesma. A ferramenta ? validada por casos de testes dados pelo International Conference On Computer Aided Design (ICCAD) 2017

SANSCrypt: A Sporadic-Authentication-Based Sequential Logic Encryption Scheme

We propose SANSCrypt, a novel sequential logic encryption scheme to protect integrated circuits against reverse engineering. Previous sequential encryption methods focus on modifying the circuit state machine such that the correct functionality can be accessed by applying the correct key sequence only once. Considering the risk associated with one-time authentication, SANSCrypt adopts a new temporal dimension to logic encryption, by requiring the user to sporadically perform multiple authentications according to a protocol based on pseudo-random number generation. Analysis and validation results on a set of benchmark circuits show that SANSCrypt offers a substantial output corruptibility if the key sequences are applied incorrectly. Moreover, it exhibits an exponential resilience to existing attacks, including SAT-based attacks, while maintaining a reasonably low overhead.Comment: This paper has been accepted at the 28th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC

Calculation Methodology for Flexible Arithmetic Processing

Paper submitted to the IFIP International Conference on Very Large Scale Integration (VLSI-SOC), Darmstadt, Germany, 2003.A new operation model of flexible calculation that allows us to adjust the operation delay depending on the available time is presented. The operation method design uses look-up tables and progressive construction of the result. The increase in the operators’ granularity opens up new possibilities in calculation methods and microprocessor design. This methodology, together with the advances in technology, enables the functions of an arithmetic unit to be implemented on the basis of techniques based on stored data that provide quality results and systematization in the implementation. The proposed techniques are applied in the design of a multiplier operator. We report an evaluation of the architecture in area, delay and computation error, as well as a suitable implementation of an application example in FPGA to validate the design.This work is being backed by grant DPI2002-04434-C04-01 from the Ministerio de Ciencia y Tecnología of the Spanish Government

ALICE ITS 3: the first truly cylindrical inner tracker

The high integration density of MAPS, with silicon sensor and readout electronics implemented in the same device, allows very thin structures with a greatly reduced material budget. Thicknesses of $\mathcal{O}$(50~$\mu$m), values at which silicon chips become flexible, are readily used in many applications. In addition, MAPS can be produced in sensors of wafer size by a process known as stitching. This in turn allows to build detector elements that are large enough to cover full tracker half-layers with single bent sensors. The ALICE ITS~3 project is planning to build a new vertex tracker based on truly cylindrical wafer-scale sensors, with <0.05\% X/X$_{0}$ per layer and located as close as 18 mm to the interaction point. R\&D on all project aspects (including mechanics for bent wafer-scale devices, test beams of bent MAPS, design of stitched sensors) is rapidly progressing with the aim for installation during LHC long shutdown 3 (2025--2027). This contribution summarises the project motivation, its R\&D schedule, and will show selected highlights of recently accomplished project milestones, including full-scale engineering prototypes with dummy chips and small-scale, fully functional assemblies of functional, bent MAPS.Comment: 4 pages, 3 figures, proceedings at the 12th International Conference on Position Sensitive Detectors - PSD12 12-17 September, 2021, Birmingham, U.

Feasible delay bound definition

11th International Conference on Very Large Scale Integration ofSystems-on-Chip (VLSI-SOC'Ol) December 3-5, 2001, Montpellier, FranceInternational audienceMinimizing the number of iterations when satisfying performance constraints in IC design is of fundamental importance to limit the design iterations. We present a method to determine the feasibility of delay constraint imposed on circuit path. From a layout oriented study of the path delay distribution, we show how to obtain the upper and lower bounds of the delay of combinatorial paths. Then we characterise these bounds and present a method to determine, , the average weighted loading factor allowing to satisfy the delay constraint. Example of application is given on different ISCAS circuits