Metastability-Containing Circuits

In digital circuits, metastability can cause deteriorated signals that neither are logical 0 or logical 1, breaking the abstraction of Boolean logic. Unfortunately, any way of reading a signal from an unsynchronized clock domain or performing an analog-to-digital conversion incurs the risk of a metastable upset; no digital circuit can deterministically avoid, resolve, or detect metastability (Marino, 1981). Synchronizers, the only traditional countermeasure, exponentially decrease the odds of maintained metastability over time. Trading synchronization delay for an increased probability to resolve metastability to logical 0 or 1, they do not guarantee success. We propose a fundamentally different approach: It is possible to contain metastability by fine-grained logical masking so that it cannot infect the entire circuit. This technique guarantees a limited degree of metastability in---and uncertainty about---the output. At the heart of our approach lies a time- and value-discrete model for metastability in synchronous clocked digital circuits. Metastability is propagated in a worst-case fashion, allowing to derive deterministic guarantees, without and unlike synchronizers. The proposed model permits positive results and passes the test of reproducing Marino's impossibility results. We fully classify which functions can be computed by circuits with standard registers. Regarding masking registers, we show that they become computationally strictly more powerful with each clock cycle, resulting in a non-trivial hierarchy of computable functions

Feasibility study of 5G low-latency packet radio communications without preambles

This thesis deals with the feasibility of having lower latency for radio communication of short packets, which is the major traffic in the fifth generation (5G) of cellular systems. We will examine the possibility of using turbo synchronization instead of using a long preamble, which is needed for Data-Aided (DA) synchronization. The idea behind this is that short packets are required in low-latency applications. The overhead of preambles is very significant in case of short packets. Turbo synchronization allows to work with short or null preambles. The simulations will be run for a turbo synchronizer which has been implemented according to the Expectation Maximization (EM) formulation of the problem. The simulation results show that the implemented turbo synchronizer outperforms or attains the DA synchronizer in terms of reliability, accuracy and acquisition range for carrier phase synchronization. It means that the idea of eliminating the preamble from the short packet seems practical. The only downward is that there is a packet size limitation for the effective functionality of turbo synchronizer. Simulations indicate that the number of transmitted symbols should be higher than 128 coded symbols

The effect of forgetting on the performance of a synchronizer

AbstractWe study variants of the α-synchronizer by Awerbuch (1985) within a distributed message passing system with probabilistic message loss. The purpose of a synchronizer is to maintain a virtual (lock-step) round structure, which simplifies the design of higher-level distributed algorithms. The underlying idea of an α-synchronizer is to let processes continuously exchange round numbers and to allow a process to proceed to the next round only after it has witnessed that all processes have already started the current round.In this work, we study the performance of several synchronizers in an environment with probabilistic message loss. In particular, we analyze how different strategies of forgetting affect the round durations. The synchronizer variants considered differ in the times when processes discard part of their accumulated knowledge during the execution. Possible applications can be found, e.g., in sensor fusion, where sensor data become outdated and thus invalid after a certain amount of time.For all synchronizer variants considered, we develop corresponding Markov chain models and quantify the performance degradation using both analytic approaches and Monte-Carlo simulations. Our results allow to explicitly calculate the asymptotic behavior of the round durations: While in systems with very reliable communication the effect of forgetting is negligible, the effect is more profound in systems with less reliable communication. Our study thus provides computationally efficient bounds on the performance of the (non-forgetting) α-synchronizer and allows to quantitatively assess the effect accumulated knowledge has on the performance

Fast wait-free symmetry breaking in distributed systems

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1993.Includes bibliographical references (leaves 32-33).by Mark Anthony Shawn Smith.M.S

Method and apparatus for decoding compatible convolutional codes

This invention relates to learning decoders for decoding compatible convolutional codes. The decoder decodes signals which have been encoded by a convolutional coder and allows performance near the theoretical limit of performance for coded data systems. The decoder includes a sub-bit shift register wherein the received sub-bits are entered after regeneration and shifted in synchronization with a clock signal recovered from the received sub-bit stream. The received sub-bits are processed by a sub-bit decision circuit, entered into a sub-bit shift register, decoded by a decision circuit, entered into a data shift register, and updated to reduce data errors. The bit decision circuit utilizes stored sub-bits and stored data bits to determine subsequent data-bits. Data errors are reduced by using at least one up-date circuit

Scalable low latency consensus for blockchains

Tese de mestrado, Segurança Informática, Universidade de Lisboa; Faculdade de Ciências, 2021State machine replication (SMR) is a classical technique to implement consistent and fault­tolerant replicated services. This type of system is usually built on top of consensus protocols that have high throughput but have problems scaling to settings with a large number of participants or wide­area sce narios due to the required number of messages exchanged to reach a consensus. We propose ProBFT (Probabilistic Byzantine Fault Tolerance), a consensus protocol specifically de signed to tackle the scalability problem of BFT protocols. ProBFT is a consensus protocol with optimal latency (three communication steps, as in PBFT) but with a reduced number of messages exchanged in each phase (O(n √ n) instead of PBFT’s O(n 2 )). ProBFT is a probabilistic protocol built on top of well­known primitives, such as probabilistic Byzantine quorums and verifiable random functions, which provides high probabilities of safety and liveness when the overwhelming majority of replicas is correct. We also propose a state machine replication protocol called PROBER (PRObabilistic ByzantinE Replication) that builds on top of two consensus protocols, ProBFT and PBFT. PROBER makes use of ProBFT to provide fast and probabilistic replies to the clients and uses PBFT to eventually determinis tically commit the history of operations guaranteeing that the system will not roll back the requests after such commit. This periodic deterministic commit allows the clients to enjoy the low latency provided by ProBFT while still having the guarantees provided by a deterministic protocol. We provide a detailed description of both protocols and analyse the probabilities for safety and live ness depending on the current number of Byzantine replicas

Error Containment in the Presence of Metastability

Error containment is an important concept in fault tolerant system design, and techniques like voting are applied to mask erroneous outputs, thus preventing their propagation. In this presentation we will use the example of DARTS, a fault-tolerant distributed clock generation scheme in hardware, to demonstrate that metastability is a substantial threat to error containment. We will illustrate how metastability can originate and propagate such that a single fault may upset the system. The main conclusion is that modeling efforts on all design levels are definitely required in order to mitigate and quantify the deteriorating effect of metastability on system dependability

Study of a navigation and traffic control technique employing satellites. Volume 3 - User hardware Interim report

User hardware configurations and requirements for navigation and air traffic control technique using satellite

Characterization of real-time computers

A real-time system consists of a computer controller and controlled processes. Despite the synergistic relationship between these two components, they have been traditionally designed and analyzed independently of and separately from each other; namely, computer controllers by computer scientists/engineers and controlled processes by control scientists. As a remedy for this problem, in this report real-time computers are characterized by performance measures based on computer controller response time that are: (1) congruent to the real-time applications, (2) able to offer an objective comparison of rival computer systems, and (3) experimentally measurable/determinable. These measures, unlike others, provide the real-time computer controller with a natural link to controlled processes. In order to demonstrate their utility and power, these measures are first determined for example controlled processes on the basis of control performance functionals. They are then used for two important real-time multiprocessor design applications - the number-power tradeoff and fault-masking and synchronization