Very-high-frequency low-voltage power delivery

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 217-223).Power conversion for the myriad low-voltage electronic circuits in use today, including portable electronic devices, digital electronics, sensors and communication circuits, is becoming increasingly challenging due to the desire for lower voltages, higher conversion ratios and higher bandwidth. Future computation systems also pose a major challenge in energy delivery that is difficult to meet with existing devices and design strategies. To reduce interconnect bottlenecks and enable more flexible energy utilization, it is desired to deliver power across interconnects at high voltage and low current with on- or over-die transformation to low voltage and high current, while providing localized voltage regulation in numerous zones. This thesis introduces elements for hybrid GaN-Si dc-de power converters operating at very high frequencies (VHF, 30-300 MHz) for low-voltage applications. Contributions include development of a new VHF frequency multiplier inverter suitable for step-down power conversion, and a Si CMOS switched-capacitor step-down rectifier. These are applied to develop a prototype GaN-Si hybrid dc-dc converter operating at 50 MHz. Additionally, this thesis exploits these elements to propose an ac power delivery architecture for low-voltage electronics in which power is delivered across the interconnect to the load at VHF ac, with local on-die transformation and rectification to dc. With the proposed technologies and emerging passives, it is predicted that the ac power delivery system can achieve over 90 % efficiency with greater than 1 W/mm² power density and 5:1 voltage conversion ratio. A prototype system has been designed and fabricated using a TSMC 0.25 [mu]m CMOS process to validate the concept. It operates at 50 MHz with output power of 4 W. The prototype converter has 8:1 voltage conversion ratio with input voltage of 20 V and output voltage of 2.5 V. To the author's best knowledge, this is the first ac power delivery architecture for low-voltage electronics ever built and tested.by Wei Li.Ph.D

Control solutions for multiphase permanent magnet synchronous machine drives applied to electric vehicles

207 p.En esta tesis se estudia la utilización de un accionamiento eléctrico basado en una máquina simétrica dual trifásica aplicada al sistema de propulsión de un vehículo eléctrico. Dicho accionamiento está basado en una máquina síncrona de imanes permanentes interiores. Además, dispone de un bus CC con una configuración en cascada. Por otra parte, se incorpora un convertidor CC/CC entre el módulo de baterías y el inversor de seis fases para proveer el vehículo con capacidades de carga rápida, y evitando al mismo tiempo la utilización de semiconductores de potencia con altas tensiones nominales. En este escenario, el algoritmo de control debe hacer frente a las no linealidades de la máquina, proporcionando un comando de consigna preciso para todo el rango de par y velocidad del convertidor. Por lo tanto, deben tenerse en cuenta los efectos de acoplamiento cruzado entre los devanados, y la tensión de los condensadores de enlace en cascada debe controlarse y equilibrarse activamente. En vista de ello, los autores proponen un novedoso enfoque de control que proporciona todas estas funcionalidades. La propuesta se ha validado experimentalmente en un prototipo a escala real de accionamiento eléctrico de 70 kW, probado en un laboratorio y en un vehículo eléctrico en condiciones reales de conducción.Tecnali

Energy Harvesting for Self-Powered Wireless Sensors

A wireless sensor system is proposed for a targeted deployment in civil infrastructures (namely bridges) to help mitigate the growing problem of deterioration of civil infrastructures. The sensor motes are self-powered via a novel magnetic shape memory alloy (MSMA) energy harvesting material and a low-frequency, low-power rectifier multiplier (RM). Experimental characterizations of the MSMA device and the RM are presented. A study on practical implementation of a strain gauge sensor and its application in the proposed sensor system are undertaken and a low-power successive approximation register analog-to-digital converter (SAR ADC) is presented. The SAR ADC was fabricated and laboratory characterizations show the proposed low-voltage topology is a viable candidate for deployment in the proposed sensor system. Additionally, a wireless transmitter is proposed to transmit the SAR ADC output using on-off keying (OOK) modulation with an impulse radio ultra-wideband (IR-UWB) transmitter (TX). The RM and SAR ADC were fabricated in ON 0.5 micrometer CMOS process. An alternative transmitter architecture is also presented for use in the 3-10GHz UWB band. Unlike the IR-UWB TX described for the proposed wireless sensor system, the presented transmitter is designed to transfer large amounts of information with little concern for power consumption. This second method of data transmission divides the 3-10GHz spectrum into 528MHz sub-bands and "hops" between these sub-bands during data transmission. The data is sent over these multiple channels for short distances (?3-10m) at data rates over a few hundred million bits per second (Mbps). An UWB TX is presented for implementation in mode-I (3.1-4.6GHz) UWB which utilizes multi-band orthogonal frequency division multiplexing (MB-OFDM) to encode the information. The TX was designed and fabricated using UMC 0.13 micrometer CMOS technology. Measurement results and theoretical system level budgeting are presented for the proposed UWB TX

Modeling and Monitoring of the Dynamic Response of Railroad Bridges using Wireless Smart Sensors

Railroad bridges form an integral part of railway infrastructure in the USA, carrying approximately 40 % of the ton-miles of freight. The US Department of Transportation (DOT) forecasts current rail tonnage to increase up to 88 % by 2035. Within the railway network, a bridge occurs every 1.4 miles of track, on average, making them critical elements. In an effort to accommodate safely the need for increased load carrying capacity, the Federal Railroad Association (FRA) announced a regulation in 2010 that the bridge owners must conduct and report annual inspection of all the bridges. The objective of this research is to develop appropriate modeling and monitoring techniques for railroad bridges toward understanding the dynamic responses under a moving train. To achieve the research objective, the following issues are considered specifically. For modeling, a simple, yet effective, model is developed to capture salient features of the bridge responses under a moving train. A new hybrid model is then proposed, which is a flexible and efficient tool for estimating bridge responses for arbitrary train configurations and speeds. For monitoring, measured field data is used to validate the performance of the numerical model. Further, interpretation of the proposed models showed that those models are efficient tools for predicting response of the bridge, such as fatigue and resonance. Finally, fundamental software, hardware, and algorithm components are developed for providing synchronized sensing for geographically distributed networks, as can be found in railroad bridges. The results of this research successfully demonstrate the potentials of using wirelessly measured data to perform model development and calibration that will lead to better understanding the dynamic responses of railroad bridges and to provide an effective tool for prediction of bridge response for arbitrary train configurations and speeds.National Science Foundation Grant No. CMS-0600433National Science Foundation Grant No. CMMI-0928886National Science Foundation Grant No. OISE-1107526National Science Foundation Grant No. CMMI- 0724172 (NEESR-SD)Federal Railroad Administration BAA 2010-1 projectOpe

Microwave CMOS VCOs and Front-Ends - using integrated passives on-chip and on-carrier

The increasing demand for high data rates in wireless communication systems is increasing the requirements on the transceiver front-ends, as they are pushed to utilize more and wider bands at higher frequencies. The work in this thesis is focused on receiver front-ends composed of Low Noise Amplifiers (LNAs), Mixers, and Voltage Controlled Oscillators (VCOs) operating at microwave frequencies. Traditionally, microwave electronics has used exclusive and more expensive semiconductor technologies (III-V materials). However, the rapid development of consumer electronics (e.g. video game consoles) the last decade has pushed the silicon CMOS IC technology towards even smaller feature sizes. This has resulted in high speed transistors (high fT and fmax) with low noise figures. However, as the breakdown voltages have decreased, a lower supply voltage must be used, which has had a negative impact on linearity and dynamic range. Nonetheless, todays downscaled CMOS technology is a feasible alternative for many microwave and even millimeter wave applications. The low quality factor (Q) of passive components on-chip usually limits the high frequency performance. For inductors realized in a standard CMOS process the substrate coupling results in a degraded Q. The quality factor can, however, be improved by moving the passive components off-chip and integrating them on a low loss carrier. This thesis therefore features microwave front-end and VCO designs in CMOS, where some designs have been flip-chip mounted on carriers featuring high Q inductors and low loss baluns. The thesis starts with an introduction to wireless communication, receiver architectures, front-end receiver blocks, and low loss carrier technology, followed by the included papers. The six included papers show the capability of CMOS and carrier technology at microwave frequencies: Papers II, III, and VI demonstrate fully integrated CMOS circuit designs. An LC-VCO using an accumulation mode varactor is presented in Paper II, a QVCO using 4-bit switched tuning is shown in Paper III, and a quadrature receiver front-end (including QVCO) is demonstrated in paper VI. Papers I and IV demonstrate receiver front-ends using low loss baluns on carrier for the LO and RF signals. Paper IV also includes a front-end using single-ended RF input which is converted to differential form in a novel merged LNA and balun. A VCO demonstrating the benefits of a high Q inductor on carrier is presented in Paper V

A Multi-level Multi-Modular Flying Capacitor Voltage Source Converter for High Power Applications

Two vital and dynamically changing issues are arising in the electric grid - an increase in electrical power demand, and subsequent reduction in power quality. Power electronics based solutions such as the Static Synchronous Compensator are increasingly deployed to mitigate power quality issues while High Voltage DC Transmission converters are currently installed to support the existing grid transmission capacity. Both applications require high power and high voltage power converters using switching devices with limited voltage ratings. The advent of Modular Multilevel Converters (MMC) is one of the recent responses to this need. These use half or full H-bridge circuits stacked up to form a chain, and hence can withstand high voltages using lower-rated switching devices. This thesis introduces a new member into the MMC family, i.e the Modular Multi-level Flying Capacitor Converter (MMFCC). This uses a three-level flying capacitor full-bridge circuit as a sub-module and offers features of modularity, scalability and fault tolerance. The choice of FC topology in place of the simple H-bridge stems from the FC’s ability to offer two extra voltage levels in the sub-module output and hence more degrees of freedom per module in controlling the voltage waveform. A three-level full-bridge FC sub-module uses three capacitors - an outer one for supporting the sub-module voltage, and two inner floating ones with half of the outer one’s capacitance and voltage rating. This use of slightly more complex FC sub-modules gives the benefits of a modular structure but without using twice as many sub-modules with their associated capacitors for the same total voltage. The thesis presents the principles of this topology, switching states redundancies and a method for capacitor voltage balancing. Also discussed are: the configuration of MMCC including the MMFCC in Single-Star Bridge-Cell (SSBC) or Single-Delta Bridge-Cell (SDBC) for FACTS and Battery Energy Storage System (BESS) applications; and Double-Star Chopper-Cell (DSCC) or Double-Star Bridge-Cell (DSBC) for HVDC systems. A novel overlapping hexagon pulse width modulation scheme is introduced and discussed for switching control of the MMFCC. This uses multiple hexagons all centred on one point, the same in number as the cascaded FC sub-modules, which are phase displaced relative to each other. The approach simplifies the modulation algorithm and brings flexibility in shaping the output voltage waveforms for different applications. An MMFCC experimental rig was designed and built in-house to validate some of the simulation results obtained for the modulation of this new topology. Details of the rig as well as results captured are discussed

Ultra-low power receivers for wireless sensor networks

In wireless sensor network applications, low-power operation of the wireless receiver is critical. To address this need an ultra-low power Binary Frequency Shift Keying (BFSK) receiver using the super-regenerative architecture is developed. A prototype receiver is built and tested for operation in the 900 MHz ISM band. Lab measurements show power consumption as low as 244 μW with a sensitivity of -84 dBm while operating at 250 kbps. A second test chip designed to operate at 2.4 GHz improves on the previous design by adding full digital control and calibration. The 2.4 GHz receiver consumes 215 μW while operating at 250 kbps and shows a 12 dB improvement in sensitivity over the original design. The entire receiver has an energy consumption of only 0.175 nJ/b while operating at 2 Mbps

Radiation Tolerant Electronics, Volume II

Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade.After the success of the first Special Issue on Radiation Tolerant Electronics, the current Special Issue features thirteen articles highlighting recent breakthroughs in radiation tolerant integrated circuit design, fault tolerance in FPGAs, radiation effects in semiconductor materials and advanced IC technologies and modelling of radiation effects