FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of 433.80 μV/mA and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of 1 μs. The total current consumption is 17.88 μA (for a 0.9 V supply voltage).Ministerio de Economía y Competitividad TEC2015-71072-C3-3-RConsejería de Economía, Innovación y Ciencia. Junta de Andalucía P12-TIC-186

Design of a Low Power External Capacitor-Less Low-Dropout Regulator with Gain-Compensated Error Amplifier

This thesis introduces a gain-compensated external capacitor-less low-dropout voltage regulator with total 5.7 uA quiescent current at all load conditions. The two-stage gain-compensated error amplifier is implemented with a cross-couple pair negative resistor to make the LDO achieve higher gain (> 50 dB) with very low bias current (< 1.3 uA). The LDO can achieve 52 dB loop gain at no load condition, 64 dB at 1 mA and 54 dB at 100 mA load. During transients (0 A to 100 mA) the undershoot is optimized to 98.6 mV with 100 ns rising and falling time through a differentiator circuit to boost the LDO’s transient response. The phase margin of the proposed LDO is 55◦ at 1 mA and 79.27◦ at max load (100 mA). Figure of merit (FOM) of this work is 2.79 fs which is very small

Full On-chip low dropout voltage regulator with an enhanced transient response for low power systems

A full on chip low Dropout Voltage Regulator (LDO) with fast transient response and small capacitor compensation circuit is proposed. The novel technique is implemented to detect the variation voltage at the output of LDO and enable the proposed fast detector amplifier (FDA) to improve load transient response of 50mA load step. The large external capacitor used in Conventional LDO Regulators is removed allowing for greater power system integration for system-on-chip (SoC) applications. The 1.6-V Full On-Chip LDO voltage regulator with a power supply of 1.8 V was designed and simulated in the 0.18µm CMOS technology, consuming only 14 µA of ground current with a fast settling-time LNR(Line Regulation) and LOR(Load regulation) of 928ns and 883ns respectively while the rise and fall times in LNR and LOR is 500ns

Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications

abstract: The increased adoption of Internet-of-Things (IoT) for various applications like smart home, industrial automation, connected vehicles, medical instrumentation, etc. has resulted in a large scale distributed network of sensors, accompanied by their power supply regulator modules, control and data transfer circuitry. Depending on the application, the sensor location can be virtually anywhere and therefore they are typically powered by a localized battery. To ensure long battery-life without replacement, the power consumption of the sensor nodes, the supply regulator and, control and data transmission unit, needs to be very low. Reduction in power consumption in the sensor, control and data transmission is typically done by duty-cycled operation such that they are on periodically only for short bursts of time or turn on only based on a trigger event and are otherwise powered down. These approaches reduce their power consumption significantly and therefore the overall system power is dominated by the consumption in the always-on supply regulator. Besides having low power consumption, supply regulators for such IoT systems also need to have fast transient response to load current changes during a duty-cycled operation. Supply regulation using low quiescent current low dropout (LDO) regulators helps in extending the battery life of such power aware always-on applications with very long standby time. To serve as a supply regulator for such applications, a 1.24 µA quiescent current NMOS low dropout (LDO) is presented in this dissertation. This LDO uses a hybrid bias current generator (HBCG) to boost its bias current and improve the transient response. A scalable bias-current error amplifier with an on-demand buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. Switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA for a low-ESR output capacitor range of 1 - 47µF. Designed in a 0.25 µm CMOS process, the LDO has an output voltage range of 1V – 3V, a dropout voltage of 240 mV, and a core area of 0.11 mm2.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Output-Capacitorless CMOS LDO Regulator Based on High Slew-Rate Current-Mode Transconductance Amplifier

A low quiescent current output-capacitorless CMOS LDO regulator based on a high slew-rate current-mode transconductance amplifier (CTA) as an error amplifier is presented. Load transient characteristic of the proposed LDO is improved even at low quiescent currents, by using a local common-mode feedback (LCMFB) in the proposed CTA. This provides an increase in the order of transfer characteristic of the circuit, thereby enhancing the slew-rate at the gate of pass transistor. The proposed CTA-based LDO topology has been designed and post-layout simulated in HSPICE, in a 0.18 μm CMOS process to supply a load current between 0-100 mA. Postlayout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10-100 pF.Postprint (published version

3중 샘플링 방식 델타-시그마 ADC를 이용한 디지털 Capacitive MEMS 마이크로폰

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 김수환.본 논문에서는 트리플 샘플링 적분기를 사용한 Capacitive 방식의 MEMS 마이크로폰이 제시되었다. 트리플 샘플링은 델타-시그마 방식의 아날로그-디지털 변환기의 첫 번째 적분기에 사용되었고 크게 두 가지의 동작으로 구분된다. 첫 번째로 적분기의 입력에서 반주기 지연 차동 입력을 빼서 신호 크기를 2배로 만들는 방식. 두 번째로 DAC의 피드백 커패시터를 샘플링 커패시터로 사용하여 입력 전압을 추가로 증가시키는 방식이다. 추가적으로 기존에서 샘플링 커패시터를 증가시켜 신호의 크기를 증폭시키는 방식과 결합하여 실수배의 이득을 얻을 수 있다. 또한 추가적인 커패시터, 타이밍, 전류 소모 없이 구조 변경만으로 이를 달성하였기 때문에 별다른 trade-off 없이 신호의 크기를 증폭시킬 수 있었다. 추가적으로 트리플 샘플링 방식의 적분기 신호 전달 함수 및 잡음 분석 또한 포함하였다. 우리의 readout 회로는 공급 전압이 1.8V인 0.18 m CMOS 공정으로 구현하였고 single-ended capacitive MEMS 트랜스듀서를 사용하여 측정하였다. 전류 소모량은 520 μA 이다. 마이크로폰은 A-weighted 신호 대 잡음 비는 62.1 dBA, 음향 과부하 지점은 115 dB SPL을 달성하였고 칩의 die size는 0.98〖"mm" 〗^2 이다.A triple-sampling ΔΣ ADC can replace the programmable-gain amplifier commonly used in the readout circuit for a digital capacitive MEMS microphone. The input voltage can then be multiplied by subtracting a further half-period delayed differential input and using the feedback capacitor of the DAC as a sampling capacitor. This triple-sampling technique results in a readout circuit with sensitivity and noise performance comparable to recent designs, but with a reduced power requirement. CMRR improvement is achieved by subtracting differential inputs and superior noise performance compare to conventional structure, as amplifier noise and DAC kT/C noise is not amplified by triple-sampling structure while the signal is increased by its gain. Triple-sampling also can be operated as a single-to-differential circuit. A MEMS microphone incorporating this readout circuit, fabricated in a 0.18μm CMOS process, achieved an A-weighted SNR of 62.1 dBA at 94 dB SPL with 520 μA current consumption, to which triple-sampling was shown to contribute 4.5 dBA.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.1.1 MEMS MICROPHONE TRENDS 1 1.1.2 TYPE OF MEMS MICROPHONES 4 1.1.3 PREVIOUS WORKS 7 1.2 MEMS MICROPHONE BASIC TERMS 9 1.3 THESIS ORGANIZATION 12 CHAPTER 2 SYSTEM OVERVIEW 13 2.1 SYSTEM ARCHITECTURE 13 CHAPTER 3 INTERFACE CIRCUITS AND POWER MANAGEMENT CIRCUITS 16 3.1 PSEUDO-DIFFERENTIAL SOURCE FOLLOWER 17 3.2 CHARGE PUMP 19 3.3 LOW DROPOUT REGULATOR 22 3.3.1 DESIGN CONSIDERATION OF LOW DROPOUT REGULATOR 22 3.3.2 IMPLEMENTATION OF LOW DROPOUT REGULATOR 26 CHAPTER 4 TRIPLE-SAMPLING DELTA-SIGMA ADC 31 4.1 BASIC OF DELTA-SIGMA ADC 31 4.2 IMPLEMENTATION OF TRIPLE-SAMPLING DELTA-SIGMA MODULATOR 37 4.2.1 CONVENTIONAL 1ST INTEGRATOR STRUCTURE 37 4.2.2 CROSS-SAMPLING 1ST INTEGRATOR 40 4.2.3 TRIPLE-SAMPLING 1ST INTEGRATOR 43 4.2.4 STF ANALYSIS OF TRIPLE-SAMPLING 1ST INTEGRATOR 47 4.2.5 THERMAL NOISE ANALYSIS OF TRIPLE-SAMPLING 1ST INTEGRATOR 51 4.2 CIRCUIT IMPLEMENTATION OF DELTA-SIGMA ADC 57 CHAPTER 5 MEASUREMENT RESULTS 64 5.1 MEASUREMENT ENVIRONMENT 64 5.2 MEASUREMENT RESULTS 67 5.3 PERFORMANCE SUMMARY 72 CHAPTER 6 CONCLUSION 74 BIBLIOGRAPHY 76 한글초록 79박

Analysis on Supercapacitor Assisted Low Dropout (SCALDO) Regulators

State-of-the-art electronic systems employ three fundamental techniques for DC-DC converters: (a) switch-mode power supplies (SMPS); (b) linear power supplies; (c) switched capacitor (charge pump) converters. In practical systems, these three techniques are mixed to provide a complex, but elegant, overall solution, with energy efficiency, effective PCB footprint, noise and transient performance to suit different electronic circuit blocks. Switching regulators have relatively high end-to-end efficiency, in the range of 70 to 93%, but can have issues with output noise and EMI/RFI emissions. Switched capacitor converters use a set of capacitors for energy storage and conversion. In general, linear regulators have low efficiencies in the range 30 to 60%. However, they have outstanding output characteristics such as low noise, excellent transient response to load current fluctuations, design simplicity and low cost design which are far superior to SMPS. Given the complex situation in switch-mode converters, low dropout (LDO) regulators were introduced to address the equirements of noise-sensitive and fast transient loads in portable devices. A typical commercial off-the-shelf LDO has its input voltage slightly higher than the desired regulated output for optimal efficiency. The approximate efficiency of a linear regulator, if the power consumed by the control circuits is negligible, can be expressed by the ratio of Vo/Vin. A very low frequency supercapacitor circulation technique can be combined with commercial low dropout regulator ICs to significantly increase the end-to-end efficiency by a multiplication factor in the range of 1.33 to 3, compared to the efficiency of a linear regulator circuit with the same input-output voltages. In this patented supercapacitor-assisted low dropout (SCALDO) regulator technique developed by a research team at the University of Waikato, supercapacitors are used as lossless voltage droppers, and the energy reuse occurs at very low frequencies in the range of less than ten hertz, eliminating RFI/EMI concerns. This SCALDO technique opens up a new approach to design step-down, DC-DC converters suitable for processor power supplies with very high end-to-end efficiency which is closer to the efficiencies of practical switching regulators, while maintaining the superior output specifications of a linear design. Furthermore, it is important to emphasize that the SCALDO technique is not a variation of well-known switched capacitor DC-DC converters. In this thesis, the basic SCALDO concept is further developed to achieve generalised topologies, with the relevant theory that can be applied to a converter with any input-output step-down voltage combination. For these generalised topologies, some important design parameters, such as the number of supercapacitors, switching matrix details and efficiency improvement factors, are derived to form the basis of designing SCALDO regulators. With the availability of commercial LDO ICs with output current ratings up to 10 A, and thin-prole supercapacitors with DC voltage ratings from 2.3 to 5.5 V, several practically useful, medium-current SCALDO prototypes: 12V-to-5V, 5V-to-2V, 5.5V-to-3.3V have been developed. Experimental studies were carried out on these SCALDO prototypes to quantify performance in terms of line regulation, load regulation, efficiency and transient response. In order to accurately predict the performance and associated waveforms of the individual phases (charge, discharge and transition) of the SCALDO regulator, Laplace transform-based theory for supercapacitor circulation is developed, and analytical predictions are compared with experimental measurements for a 12V-to-5V prototype. The analytical results tallied well with the practical waveforms observed in a 12V-to-5V converter, indicating that the SCALDO technique can be generalized to other versatile configurations, and confirming that the simplified assumptions used to describe the circuit elements are reasonable and justifiable. After analysing the performance of several SCALDO prototypes, some practical issues in designing SCALDO regulators have been identified. These relate to power losses and implications for future development of the SCALDO design

Efficiency Improvement of LDO Output Based Linear Regulator With Supercapacitor Energy Recovery – A versatile new technique with an example of a 5V to 1.5V version

Supercapacitors are used in various industrial applications and the supercapacitors technology is gradually progressing into a mature state. Common applications of supercapacitors are in electric vehicles, hybrid electric vehicles, uninterruptible power supply (UPS) and in portable devices such as cellular phones and laptops. The capacitance values range from fractional Farads to few thousand Farads and their continuos DC voltage ratings are from 2V to 6V. At University of Waikato, a team works on using supercapacitors for improving the efficiency of linear voltage regulators. In particular, this patented technique aims at combining off the shelfs LDO ICs and a supercapacitor array for improving end to end efficiency of linear regulator. My work is aimed at developing the theoretical background and designing prototype circuitry for a voltage regulator for the case of unregulated input supply is more than 3 times of the minimum input voltage requirement of the LDO which is applicable for a 5V to 1.5V regulator. Experimental results are indicated with future suggestions for improvement

Design consideration in low dropout voltage regulator for batteryless power management unit

Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology