Optimal realizations of floating-point implemented digital controllers with finite word length considerations.

The closed-loop stability issue of finite word length (FWL) realizations is investigated for digital controllers implemented in floating-point arithmetic. Unlike the existing methods which only address the effect of the mantissa bits in floating-point implementation to the sensitivity of closed-loop stability, the sensitivity of closed-loop stability is analysed with respect to both the mantissa and exponent bits of floating-point implementation. A computationally tractable FWL closed-loop stability measure is then defined, and the method of computing the value of this measure is given. The optimal controller realization problem is posed as searching for a floating-point realization that maximizes the proposed FWL closed-loop stability measure, and a numerical optimization technique is adopted to solve for the resulting optimization problem. Simulation results show that the proposed design procedure yields computationally efficient controller realizations with enhanced FWL closed-loop stability performance

Impact of the noise on the emulated grid voltage signal in hardware-in-the-loop used in power converters

This work evaluates the impact of the input voltage noise on a Hardware-In-the-Loop (HIL) system used in the emulation of power converters. A poor signal-to-noise ratio (SNR) can compromise the accuracy and precision of the model, and even make certain techniques for building mathematical models unfeasible. The case study presents the noise effects on a digitally controlled totem-pole converter emulated with a low-cost HIL system using an FPGA. The effects on the model outputs, and the cost and influence of different hardware implementations, are evaluated. The noise of the input signals may limit the benefits of increasing the resolution of the model.This research was funded by the Spanish Ministry of Science and Innovation under Project PID2021-128941OB-I00 TRENTI–Efficient Energy Transformation in Industrial Environment

Finite Wordlength Controller Realizations using the Specialized Implicit Form

Une forme d'état implicite spécialisée est présentée pour étudier les effets de l'implantation en précision finie des régulateurs. Cette forme permet une description macroscopique des algorithmes à implanter. Elle constitue un canevas unificateur permettant de décrire les différentes structures utilisées pour l'implantation, telles que les réalisations avec l'opérateur delta, la forme directe II en rho, la forme d'état-observateur et bien d'autres formes qui sont d'habitude traitées séparément dans la littérature. Différentes mesures quantifiant les effets de l'implantation sur le comportement en boucle fermée sont définis dans ce contexte. Elles concernent aussi bien la stabilité que la performance. L'écart entre la réalisation à précision infinie et la réalisation à précision finie est évaluée selon la mesure de sensibilité des coefficients et la mesure du bruit de quantification. Le problème consistant à trouver une réalisation dont l'implantation amène un minimum de dégradation peut alors est résolut numériquement. Cette approche est illustrée avec deux exemples

Finite worldlength effects in fixed-point implementations of linear systems

Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (p. 173-194).by Vinay Mohta.M.Eng

The digital implementation of control compensators : the coefficient wordlength issue

Bibliography: leaves 32-34."October, 1979."NASA Ames Grant NGL-22-009-124by Paul Moroney, Alan S. Willsky, Paul K. Houpt

Programming with Numerical Uncertainties

Numerical software, common in scientific computing or embedded systems, inevitably uses an approximation of the real arithmetic in which most algorithms are designed. In many domains, roundoff errors are not the only source of inaccuracy and measurement as well as truncation errors further increase the uncertainty of the computed results. Adequate tools are needed to help users select suitable approximations (data types and algorithms) which satisfy their accuracy requirements, especially for safety- critical applications. Determining that a computation produces accurate results is challenging. Roundoff errors and error propagation depend on the ranges of variables in complex and non-obvious ways; even determining these ranges accurately for nonlinear programs poses a significant challenge. In numerical loops, roundoff errors grow, in general, unboundedly. Finally, due to numerical errors, the control flow in the finite-precision implementation may diverge from the ideal real-valued one by taking a different branch and produce a result that is far-off of the expected one. In this thesis, we present techniques and tools for automated and sound analysis, verification and synthesis of numerical programs. We focus on numerical errors due to roundoff from floating-point and fixed-point arithmetic, external input uncertainties or truncation errors. Our work uses interval or affine arithmetic together with Satisfiability Modulo Theories (SMT) technology as well as analytical properties of the underlying mathematical problems. This combination of techniques enables us to compute sound and yet accurate error bounds for nonlinear computations, determine closed-form symbolic invariants for unbounded loops and quantify the effects of discontinuities on numerical errors. We can furthermore certify the results of self-correcting iterative algorithms. Accuracy usually comes at the expense of resource efficiency: more precise data types need more time, space and energy. We propose a programming model where the scientist writes his or her numerical program in a real-valued specification language with explicit error annotations. It is then the task of our verifying compiler to select a suitable floating-point or fixed-point data type which guarantees the needed accuracy. Sometimes accuracy can be gained by simply re-arranging the non-associative finite-precision computation. We present a scalable technique that searches for a more optimal evaluation order and show that the gains can be substantial. We have implemented all our techniques and evaluated them on a number of benchmarks from scientific computing and embedded systems, with promising results

Design of high-speed and low-power finite-word-length PID controllers.

International audienceASIC or FPGA implementation of a finite word-length PID controller requires a double expertise : in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to design configurable fixed-point PIDs to satisfy application srequiring minimal power consumption, or high control-rate, or both together. As multiply operation is the engine of PID, we experienced three algorithms : Booth, modified Booth, and a new recursive multi-bit multiplication algorithm. This later enables the construction of finely grained PID structures with bit-velvel and unit-time precsion. Such a feature permits to tailor the PID to the desired performance and power budget. All PIDs are emplemented at register-transfer-level (RTL) level as technology-independent reusable IP-cores. They are reconfigurable according to two compile-time constants : set-point word-length and latency. To make PID design easily reproducible, all necessary implementation details are provided and discussed

Roundoff noise and scaling in the digital implementation of control compensators

Bibliography: p. 52-54."August, 1981""NASA Ames ... Grant NGL-22-009-124"Paul Moroney, Alan S. Willsky, Paul K. Houpt

Low Parametric Sensitivity Realizations with relaxed L2-dynamic-range-scaling constraints

This paper presents a new dynamic-range scaling for the implementation of filters/controllers in state-space form. Relaxing the classical L2-scaling constraints by specific fixed-point considerations allows for a higher degree of freedom for the optimal L2-parametric sensitivity problem. However, overflows in the implementation are still prevented. The underlying constrained problem is converted into an unconstrained problem for which a solution can be provided. This leads to realizations which are still scaled but less sensitive