A Bang-Bang All-Digital PLL for Frequency Synthesis

abstract: Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF transceivers and ADCs. Traditionally, PLLs have been primarily analog in nature and since the development of the charge pump PLL, they have almost exclusively been analog. Recently, however, much research has been focused on ADPLLs because of their scalability, flexibility and higher noise immunity. This research investigates some of the latest all-digital PLL architectures and discusses the qualities and tradeoffs of each. A highly flexible and scalable all-digital PLL based frequency synthesizer is implemented in 180 nm CMOS process. This implementation makes use of a binary phase detector, also commonly called a bang-bang phase detector, which has potential of use in high-speed, sub-micron processes due to the simplicity of the phase detector which can be implemented with a simple D flip flop. Due to the nonlinearity introduced by the phase detector, there are certain performance limitations. This architecture incorporates a separate frequency control loop which can alleviate some of these limitations, such as lock range and acquisition time.Dissertation/ThesisM.S. Electrical Engineering 201

Design and VHDL Modeling of All-Digital PLLs

International audienceIn this paper, a VHDL model of a second-order alldigital phase-locked loop (ADPLL) based on bang-bang phase detectors is presented. The developed ADPLL is destined to be a part of a distributed clock generators based on networks of the ADPLL. The paper presents an original model and architecture of a digital multi-bit phase-frequency detector (PFD), and describes in details the VHDL modeling of metastability issues related with asynchronous operation of the digital PFD. This particular architecture of the digital PHD is required by the synchronised operation of the ADPLL network in the context of distributed clock generator. The whole ADPLL model have been validated by purely behavioral (VHDL) and mixed simulation, in which the digital PFD detector was represented by its transistorlevel model

Delay Flip-Flop (DFF) Metastability Impact on Clock and Data Recovery (CDR) and Phase-Locked Loop (PLL) Circuits

Modeling delay flip-flops for binary (e.g., Alexander) phase detectors requires paying close attention to three important timing parameters: setup time, hold time, and clock edge-to-output (or briefly C2Q time). These parameters have a critical role in determining the status of the system on the circuit level. This study provided a guideline for designing an optimum DFF for an Alexander phase detector in a clock and data recovery circuit. Furthermore, it indicated DFF timing requirements for a high-speed phase detector in a clock and data recovery circuit. The CDR was also modeled by Verilog-A, and the results were compared with Simulink model achievements. Eventually designed in 45 nm CMOS technology, for 10 Gbps random sequence, the recovered clock contained 0.136 UI and 0.15 UI peak-to-peak jitter on the falling and rising edges respectively, and the lock time was 125 ns. The overall power dissipation was 21 mW from a 1 V supply voltage. Future work includes layout design and manufacturing of the proposed design

최적 위상 검출 회로를 이용한 클럭 및 데이터 복원 회로에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 8. 김재하.Bang-bang phase detectors are widely used for today's high-speed communication circuits such as phase-locked loops (PLLs), delay-locked loops (DLLs) and clock-and-data recovery loops (CDRs) because it is simple, fast, accurate and amenable to digital implementations. However, its hard nonlinearity poses difficulties in design and analyses of the bang-bang controlled timing loops. Especially, dithering in bang-bang controlled CDRs sets conflicting requirements on the phase adjustment resolution as one tries to maximize the tracking bandwidth and minimize jitter. A fine phase step is helpful to minimize the dithering, but it requires circuits with finer resolution that consumes large power and area. In this background, this dissertation introduces an optimal phase detection technique that can minimize the effect of dithering without requiring fine phase resolution. A novel phase interval detector that looks for a phase interval enclosing the desired lock point is shown to find the optimal phase that minimizes the timing error without dithering. A digitally-controlled, phase-interpolating DLL-based CDR fabricated in 65nm CMOS demonstrates that it can achieve small area of 0.026mm^2 and low jitter of 41mUIp-p with a coarse phase adjustment step of 0.11UI, while dissipating only 8.4mW at 5Gbps. For the theoretic basis, various analysis techniques to understand bang-bang controlled timing loops are also presented. The proposed techniques are explained for both linearized loop and non-linear one, and applied to the evaluation of the proposed phase detection technique.1 Introduction 1 1.1 Motivations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Contribution and Organization . . . . . . . . . . . . . . . . . 6 2 Pseudo-Linear Analysis of Bang-Bang Controlled Loops 9 2.1 Model of a Second-Order, Bang-Bang Controlled Timing Loop . . . 9 2.2 Necessary Condition for the Pseudo-Linear Analysis . . . . . . . . . 12 2.3 Derivation of Necessity Condition for the Pseudo-Linear Analysis . . 17 2.4 A Linearized Model of the Bang-Bang Phase Detector . . . . . . . . 18 2.5 Linearized Gain of a Bang-Bang Phase Detector for Jitter Transfer and Jitter Generation Analyses . . . . . . . . . . . . . . . . . . . . . 21 2.6 Jitter Transfer and Jitter Generation Analyses . . . . . . . . . . . . 29 2.7 Linearized Gains of a Bang-bang Phase Detector for Jitter Tolerance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.8 Jitter Tolerance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 41 3 Nonlinear Analysis of Bang-Bang Controlled Loops 48 3.1 Transient Analysis of Bang-Bang Controlled Timing Loops . . . . . 48 3.2 Phase-portrait Analysis of Bang-Bang Controlled Timing Loops . . . 51 3.3 Markov-chain Analysis of Bang-Bang Controlled Timing Loops . . . 53 3.4 Analysis of Clock-and-Data Recovery Circuits . . . . . . . . . . . . . 57 3.4.1 Prediction of Bit-Error Rate . . . . . . . . . . . . . . . . . . 57 3.4.2 Eect of Transition Density . . . . . . . . . . . . . . . . . . . 58 3.4.3 Eect of Decimation . . . . . . . . . . . . . . . . . . . . . . . 61 3.4.4 Analysis of Oversampling Phase Detectors . . . . . . . . . . . 66 4 Design of Ditherless Clock and Data Recovery Circuit 75 4.1 Optimal Phase Detection . . . . . . . . . . . . . . . . . . . . . . . . 75 4.2 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.3 Analysis of the CDR with Phase Interval Detection . . . . . . . . . . 84 4.4 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.4.1 Sampling Receiver . . . . . . . . . . . . . . . . . . . . . . . . 89 4.4.2 Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.4.3 Digital Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . 95 4.4.4 Phase Locked-Loop . . . . . . . . . . . . . . . . . . . . . . . . 98 4.4.5 Phase Interpolator . . . . . . . . . . . . . . . . . . . . . . . . 99 4.5 Built-In Self-Test Circuit for Jitter Tolerance Measurement . . . . . 102 4.6 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5 Conclusion 114 References 116Docto

Influence of jitter on limit cycles in bang-bang clock and data recovery circuits

In bang-bang (BB) clock and data recovery circuits (CDR) limit cycles can occur, but these limit cycles are undesired for a good operation of the BB-CDR. Surprisingly, however, a little bit of noise in the system is beneficial, because it will quench the limit cycles. Until now, authors have always assumed that there is enough noise in a BB-CDR such that no limit cycle occurs. In this work, a pseudo-linear analysis based on describing functions is used to investigate this. In particular, the relationship between the input noise and the amplitude of eventual limit cycles is investigated. An important result of the theory is that it allows to quantify the influence of the different loop parameters on the minimal amount of input jitter needed to destroy the limit cycle. Additionally, for the case that there is not enough noise, the worst case amplitude of the limit cycle (which is unavoidable in this case) is quantified as well. The presented analysis exhibits excellent matching with time domain simulations and leads to very simple analytical expressions

LOW-JITTER AND LOW-SPUR RING-OSCILLATOR-BASED PHASE-LOCKED LOOPS

Department of Electrical EngineeringIn recent years, ring-oscillator based clock generators have drawn a lot of attention due to the merits of high area efficiency, potentially wide tuning range, and multi-phase generation. However, the key challenge is how to suppress the poor jitter of ring oscillators. There have been many efforts to develop a ring-oscillator-based clock generator targeting very low-jitter performance. However, it remains difficult for conventional architectures to achieve both low RMS jitter and low levels of reference spurs concurrently while having a high multiplication factor. In this dissertation, a time-domain analysis is presented that provides an intuitive understanding of RMS jitter calculation of the clock generators from their phase-error correction mechanisms. Based on this analysis, we propose new designs of a ring-oscillator-based PLL that addresses the challenges of prior-art ring-based architectures. This dissertation introduces a ring-oscillator-based PLL with the proposed fast phase-error correction (FPEC) technique, which emulates the phase-realignment mechanism of an injection-locked clock multiplier (ILCM). With the FPEC technique, the phase error of the voltage-controlled oscillator (VCO) is quickly removed, achieving ultra-low jitter. In addition, in the transfer function of the proposed architecture, an intrinsic integrator is involved since it is naturally based on a PLL topology. The proposed PLL can thus have low levels of reference spurs while maintaining high stability even for a large multiplication factor. Furthermore, it presents another design of a digital PLL embodying the FPEC technique (or FPEC DPLL). To overcome the problem of a conventional TDC, a low-power optimally-spaced (OS) TDC capable of effectively minimizing the quantization error is presented. In the proposed FPEC DPLL, background digital controllers continuously calibrate the decision thresholds and the gain of the error correction by the loop to be optimal, thus dramatically reducing the quantization error. Since the proposed architecture is implemented in a digital fashion, the variables defining the characteristics of the loop can be easily estimated and calibrated by digital calibrators. As a result, the performances of an ultra-low jitter and the figure-of-merit can be achieved.clos

Distributed clock generator for synchronous SoC using ADPLL network

International audienceThis paper presents a novel architecture of on-chip clock generation employing a network of oscillators synchronized by the distributed all-digital PLLs (ADPLLs). The implemented prototype has 16 clocking domains operating synchronously in a frequency range of 1.1-2.4 GHz. The synchronization error between the neighboring clock domains is less than 60 ps. The fully digital architecture of the generation offers flexibility and efficient synchronization control suitable for use in synchronous SoCs