Modeling and Optimization Algorithm for SiC-based Three-phase Motor Drive System

More electric aircraft (MEA) and electrified aircraft propulsion (EAP) becomes the important topics in the area of transportation electrifications, expecting remarkable environmental and economic benefits. However, they bring the urgent challenges for the power electronics design since the new power architecture in the electrified aircraft requires many benchmark designs and comparisons. Also, a large number of power electronics converter designs with different specifications and system-level configurations need to be conducted in MEA and EAP, which demands huge design efforts and costs. Moreover, the long debugging and testing process increases the time to market because of gaps between the paper design and implementation. To address these issues, this dissertation covers the modeling and optimization algorithms for SiC-based three-phase motor drive systems in aviation applications. The improved models can help reduce the gaps between the paper design and implementation, and the implemented optimization algorithms can reduce the required execution time of the design program. The models related to magnetic core based inductors, geometry layouts, switching behaviors, device loss, and cooling design have been explored and improved, and several modeling techniques like analytical, numerical, and curve-fitting methods are applied. With the developed models, more physics characteristics of power electronics components are incorporated, and the design accuracy can be improved. To improve the design efficiency and to reduce the design time, optimization schemes for the filter design, device selection combined with cooling design, and system-level optimization are studied and implemented. For filter design, two optimization schemes including Ap based weight prediction and particle swarm optimization are adopted to reduce searching efforts. For device selection and related cooling design, a design iteration considering practical layouts and switching speed is proposed. For system-level optimization, the design algorithm enables the evaluation of different topologies, modulation schemes, switching frequencies, filter configurations, cooling methods, and paralleled converter structure. To reduce the execution time of system-level optimization, a switching function based simulation and waveform synthesis method are adopted. Furthermore, combined with the concept of design automation, software integrated with the developed models, optimization algorithms, and simulations is developed to enable visualization of the design configurations, database management, and design results

Multipurpose self-configuration of programmable photonic circuits

[EN] Programmable integrated photonic circuits have been called upon to lead a new revolution in information systems by teaming up with high speed digital electronics and in this way, adding unique complementary features supported by their ability to provide bandwidthunconstrained analog signal processing. Relying on a common hardware implemented by two-dimensional integrated photonic waveguide meshes, they can provide multiple functionalities by suitable programming of their control signals. Scalability, which is essential for increasing functional complexity and integration density, is currently limited by the need to precisely control and configure several hundreds of variables and simultaneously manage multiple configuration actions. Here we propose and experimentally demonstrate two different approaches towards management automation in programmable integrated photonic circuits. These enable the simultaneous handling of circuit self-characterization, auto-routing, self-configuration and optimization. By combining computational optimization and photonics, this work takes an important step towards the realization of high-density and complex integrated programmable photonics.D.P.L. acknowledges funding through the Spanish MINECO Juan de la Cierva program. J.C. acknowledges funding from the ERC Advanced Grant ERC-ADG-2016-741415 UMWP-Chip and ERC-2019-POC-859927. Authors also acknowledge funding from Future MWP technologies and applications PROMETEO/2017/103, Advanced Instrumentation for World Class Microwave Photonics Research IDIFEDER/2018/031, EUIMWP CA16220, Infraestructura para caracterizacion de Chips Fotonicos EQC2018-004683-P.Pérez-López, D.; López-Hernández, A.; Dasmahapatra, P.; Capmany Francoy, J. (2020). Multipurpose self-configuration of programmable photonic circuits. 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Multipurpose silicon photonics signal processor core. Nat. Commun. 8, 636 (2017).Zhang, W. & Yao, J. Photonic integrated field-programmable disk array signal processor. Nat. Commun. 11, 406 (2020).Eberhart, J. K. R. A new optimizer using particle swarm theory. In MHS'95. Proceedings of the Sixth International Symposium on Micro Machine and Human Science (IEEE, Nagoya, Japan, 1995).Whitley, D. A genetic algorithm tutorial. Stat. Comput. 4, 65–85 (1994).Zibar, D., Wymeersch, H. & Lyubomirsky, I. Machine Learning under the spotlight. Nat. Photonics 11, 749–751 (2017).Pérez, D. Programmable integrated silicon photonics waveguide meshes: optimized designs and control algorithms. In IEEE Journal of Selected Topics in Quantum Electronics, Vol. 26 (IEEE, 2019).Pérez, D., Gasulla, I. & Capmany, J. Field-programmable photonic arrays. Opt. Express 26, 27265–27278 (2018).Pérez, D., Gasulla, I., Soref, R. & Capmany, J. Reconfigurable lattice mesh designs for programmable photonic processors. Opt. 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In Conference on Lasers and Electro-Optics (IEEE, San José, CA, 2018).Milanizadeh, M. et al. Cancelling thermal cross-talk effects in photonic integrated circuits. J. Light. Tech. 37, 1325–1332 (2019).Xie, Y., Zhuang, L. & Lowery, A. J. Picosecond optical pulse processing using a terahertz-bandwidth reconfigurable photonic integrated circuit. Nanophotonics 7, 837–852 (2018).Guan, B. et al. CMOS compatible reconfigurable silicon photonic lattice filters using cascaded unit cells for RF-photonic processing. IEEE J. Sel. Top. Quantum Electron. 20, 359–368 (2014).Doylend, J. K. et al. Hybrid III/V silicon photonic source with integrated 1D free-space beam steering. Opt. Lett. 37, 4257–4259 (2012).Burla, M. Advanced integrated optical beam forming networks for broadband phased array antenna systems, Telecommunication Engineering Faculty of Electrical Engineering, Mathematics and Computer Science. PhD. Thesis, University of Twente (2013).Wang, J. et al. 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A multi-objective particle swarm optimization algorithm based on dynamic boundary search for constrained optimization. Appl. Soft Comput. 70, 680–700 (2018).Pérez, D. et al. Thermal tuners on a silicon nitride platform. Preprint at https://arxiv.org/abs/1604.02958 (2016)

Analysis and Design Methodologies for Switched-Capacitor Filter Circuits in Advanced CMOS Technologies

Analog filters are an extremely important block in several electronic systems, such as RF transceivers, data acquisition channels, or sigma-delta modulators. They allow the suppression of unwanted frequencies bands in a signal, improving the system’s performance. These blocks are typically implemented using active RC filters, gm-C filters, or switched-capacitor (SC) filters. In modern deep-submicron CMOS technologies, the transistors intrinsic gain is small and has a large variability, making the design of moderate and high-gain amplifiers, used in the implementation of filter blocks, extremely difficult. To avoid this difficulty, in the case of SC filters, the opamp can be replaced with a voltage buffer or a low-gain amplifier (< 2), simplifying the amplifier’s design and making it easier to achieve higher bandwidths, for the same power. However, due to the loss of the virtual ground node, the circuit becomes sensitive to the effects of parasitic capacitances, which effect needs to be compensated during the design process. This thesis addresses the task of optimizing SC filters (mainly focused on implementations using low-gain amplifiers), helping designers with the complex task of designing high performance SC filters in advanced CMOS technologies. An efficient optimization methodology is introduced, based on hybrid cost functions (equation-based/simulation-based) and using genetic algorithms. The optimization software starts by using equations in the cost function to estimate the filter’s frequency response reducing computation time, when compared with the electrical simulation of the circuit’s impulse response. Using equations, the frequency response can be quickly computed (< 1 s), allowing the use of larger populations in the genetic algorithm (GA) to cover the entire design space. Once the specifications are met, the population size is reduced and the equation-based design is fine-tuned using the more computationally intensive, but more accurate, simulation-based cost function, allowing to accurately compensate the parasitic capacitances, which are harder to estimate using equations. With this hybrid approach, it is possible to obtain the final optimized design within a reasonable amount of computation time. Two methods are described for the estimation of the filter’s frequency response. The first method is hierarchical in nature where, in the first step, the frequency response is optimized using the circuit’s ideal transfer function. The following steps are used to optimize circuits, at transistor level, to replace the ideal blocks (amplifier and switches) used in the first step, while compensating the effects of the circuit’s parasitic capacitances in the ideal design. The second method uses a novel efficient numerical methodology to obtain the frequency response of SC filters, based on the circuit’s first-order differential equations. The methodology uses a non-hierarchical approach, where the non-ideal effects of the transistors (in the amplifier and in the switches) are taken into consideration, allowing the accurate computation of the frequency response, even in the case of incomplete settling in the SC branches. Several design and optimization examples are given to demonstrate the performance of the proposed methods. The prototypes of a second order programmable bandpass SC filter and a 50 Hz notch SC filter have been designed in UMC 130 nm CMOS technology and optimized using the proposed optimization software with a supply voltage of 0.9 V. The bandpass SC filter has a total power consumption of 249 uW. The filter’s central frequency can be tuned between 3.9 kHz and 7.1 kHz, the gain between -6.4 dB and 12.6 dB, and the quality factor between 0.9 and 6.9. Depending on the bit configuration, the circuit’s THD is between -54.7 dB and -61.7 dB. The 50 Hz notch SC filter has a total power consumption of 273 uW. The transient simulation of the circuit’s extracted view (C+CC) shows an attenuation of 52.3 dB in the 50 Hz interference and that the desired 5 kHz signal has a THD of -92.3 dB

Measurements, Models, Systems and Design

531 s.

Behavioral Modeling of Mixed-Mode Integrated Circuits

Open Access.-- et al.This work is partially supported by CONACyT through the grant for the sabbatical stay of the first author at University of California at Riverside, during 2009-2010. The authors acknowledge the support from UC-MEXUS-CONACYT collaboration grant CN-09-310; by Promep México under the project UATLX-PTC-088, and by Consejeria de Innovacion Ciencia y Empresa, Junta de Andalucia, Spain, under the project number TIC-2532. The third author thanks the support of the JAE-Doc program of CSIC, co-funded by FSE.Peer Reviewe

Intrinsic Hardware Evolution on the Transistor Level

This thesis presents a novel approach to the automated synthesis of analog circuits. Evolutionary algorithms are used in conjunction with a fitness evaluation on a dedicated ASIC that serves as the analog substrate for the newly bred candidate solutions. The advantage of evaluating the candidate circuits directly in hardware is twofold. First, it may speed up the evolutionary algorithms, because hardware tests can usually be performed faster than simulations. Second, the evolved circuits are guaranteed to work on a real piece of silicon. The proposed approach is realized as a hardware evolution system consisting of an IBM compatible general purpose computer that hosts the evolutionary algorithm, an FPGA-based mixed signal test board, and the analog substrate. The latter one is designed as a Field Programmable Transistor Array (FPTA) whose programmable transistor cells can be almost freely connected. The transistor cells can be configured to adopt one out of 75 different channel geometries. The chip was produced in a 0.6µm CMOS process and provides ample means for the input and output of analog signals. The configuration is stored in SRAM cells embedded in the programmable transistor cells. The hardware evolution system is used for numerous evolution experiments targeted at a wide variety of different circuit functionalities. These comprise logic gates, Gaussian function circuits, D/A converters, low- and highpass filters, tone discriminators, and comparators. The experimental results are thoroughly analyzed and discussed with respect to related work

Fast and Robust Design of CMOS VCO for Optimal Performance

The exponentially growing design complexity with technological advancement calls for a large scope in the analog and mixed signal integrated circuit design automation. In the automation process, performance optimization under different environmental constraints is of prime importance. The analog integrated circuits design strongly requires addressing multiple competing performance objectives for optimization with ability to find global solutions in a constrained environment. The integrated circuit (IC) performances are significantly affected by the device, interconnect and package parasitics. Inclusion of circuit parasitics in the design phase along with performance optimization has become a bare necessity for faster prototyping. Besides this, the fabrication process variations have a predominant effect on the circuit performance, which is directly linked to the acceptability of manufactured integrated circuit chips. This necessitates a manufacturing process tolerant design. The development of analog IC design methods exploiting the computational intelligence of evolutionary techniques for optimization, integrating the circuit parasitic in the design optimization process in a more meaningful way and developing process fluctuation tolerant optimal design is the central theme of this thesis. Evolutionary computing multi-objective optimization techniques such as Non-dominated Sorting Genetic Algorithm-II and Infeasibility Driven Evolutionary Algorithm are used in this thesis for the development of parasitic aware design techniques for analog ICs. The realistic physical and process constraints are integrated in the proposed design technique. A fast design methodology based on one of the efficient optimization technique is developed and an extensive worst case process variation analysis is performed. This work also presents a novel process corner variation aware analog IC design methodology, which would effectively increase the yield of chips in the acceptable performance window. The performance of all the presented techniques is demonstrated through the application to CMOS ring oscillators, current starved and xi differential voltage controlled oscillators, designed in Cadence Virtuoso Analog Design Environment

Evolving hardware with genetic algorithms

Genetic techniques are applied to the problem of electronic circuit design, with an emphasis on VLSI circuits. The goal is to have a tool which has the performance and flexibility to attack a wide range of problems. A genetic algorithm is used to design a circuit specified by the desired input /output characteristics. A software system is implemented to synthesize and optimize circuits using an asynchronous parallel genetic algorithm. The software is designed with object-oriented constructs in order to maintain scalability and provide for future enhancements. The system is executed on a heterogeneous network of workstations ranging from Sun Sparc Ultras to HP multiprocessors. Testing of this software is done with examples of both digital and analog CMOS VLSI circuits. Performance is measured in both the quality of the solutions and in the time it took to evolve them

Constraint-Aware, Scalable, and Efficient Algorithms for Multi-Chip Power Module Layout Optimization

Moving towards an electrified world requires ultra high-density power converters. Electric vehicles, electrified aerospace, data centers, etc. are just a few fields among wide application areas of power electronic systems, where high-density power converters are essential. As a critical part of these power converters, power semiconductor modules and their layout optimization has been identified as a crucial step in achieving the maximum performance and density for wide bandgap technologies (i.e., GaN and SiC). New packaging technologies are also introduced to produce reliable and efficient multichip power module (MCPM) designs to push the current limits. The complexity of the emerging MCPM layouts is surpassing the capability of a manual, iterative design process to produce an optimum design with agile development requirements. An electronic design automation tool called PowerSynth has been introduced with ongoing research toward enhanced capabilities to speed up the optimized MCPM layout design process. This dissertation presents the PowerSynth progression timeline with the methodology updates and corresponding critical results compared to v1.1. The first released version (v1.1) of PowerSynth demonstrated the benefits of layout abstraction, and reduced-order modeling techniques to perform rapid optimization of the MCPM module compared to the traditional, manual, and iterative design approach. However, that version is limited by several key factors: layout representation technique, layout generation algorithms, iterative design-rule-checking (DRC), optimization algorithm candidates, etc. To address these limitations, and enhance PowerSynth’s capabilities, constraint-aware, scalable, and efficient algorithms have been developed and implemented. PowerSynth layout engine has evolved from v1.3 to v2.0 throughout the last five years to incorporate the algorithm updates and generate all 2D/2.5D/3D Manhattan layout solutions. These fundamental changes in the layout generation methodology have also called for updates in the performance modeling techniques and enabled exploring different optimization algorithms. The latest PowerSynth 2 architecture has been implemented to enable electro-thermo-mechanical and reliability optimization on 2D/2.5D/3D MCPM layouts, and set up a path toward cabinet-level optimization. PowerSynth v2.0 computer-aided design (CAD) flow has been hardware-validated through manufacturing and testing of an optimized novel 3D MCPM layout. The flow has shown significant speedup compared to the manual design flow with a comparable optimization result

Synthesis of Planar Microwave Circuits based on Metamaterial Concepts through Aggressive Space Mapping

RF and microwave applications represent one of the fastest-growing segments of the high performance electronics market, where ongoing innovation is critical. Manufacturers compete intensively to meet market needs with reduced cost, size, weight and many other performance criteria demands. Under this scenario, transmission lines based on metamaterial concepts can be considered a very interesting alternative to the conventional transmission lines. They are more compact (compatible with planar manufacturing processes) and present higher degrees of design flexibility. Furthermore, metamaterial transmission lines can also provide many other unique properties not achievable with ordinary transmission lines, such as dispersion or impedance engineering. Nevertheless, the impact in the industry is still not relevant, mostly due to the complexity of the related synthesis and design procedures. These procedures are mainly based on the engineer’s experience, with the help of costly full-wave electromagnetic (EM) simulators and parameter extraction methods. The aim of this thesis is to contribute to simplify and speed up the synthesis and design procedures of artificial transmission lines. In particular, the lines obtained by periodically loading a conventional transmission line with electrically small resonators, such as split ring resonators (SSRs) or its complementary particle (CSRR). The design procedure is automated by using Space Mapping techniques. In contrast to other alternative methods, real synthesis is found from the circuit schematic (that provides a given target response) and without need of human intervention. Some efforts to make the method practical and useful have been carried out. Given a certain target response, it is determined whether it can be physically implemented with a chosen technology, and hence proceeding next to find the synthesis, or not. For this purpose, a two-step Aggressive Space Mapping approach is successfully proposed. In contrast to other methods, the real synthesis is found from certain target circuit values (corresponding to the equivalent circuit model that characterizes the structure to be synthesized). Different efforts have been carried out in order to implement a useful and practical method. Some of them were focused to determine if, given certain circuit parameters (which determine the target response) and certain given technology specifications (permittivity and height of the substrate, technology limits), that response is physically realizable (convergence region). This technique was successfully formulated and it is known as “Two-Step Aggressive Space Mapping Approach”. In this work, the latest improvements made till date, from the synthesis of basic unit cells until different applications and kinds of metamaterial-based circuits, are presented. The results are promising and prove the validity of the method, as well as its potential application to other basic cells and more complex designs. The general knowledge gained from these cases of study can be considered a good base for a coming implementation in commercial software tools, which can help to improve its competitiveness in markets, and also contribute to a more general use of this technology.Rodríguez Pérez, AM. (2014). Synthesis of Planar Microwave Circuits based on Metamaterial Concepts through Aggressive Space Mapping [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/48465TESI