Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

Thermal performance enhancement of packaging substrates with integrated vapor chamber

The first part of this research investigates the effects of copper structures, such as copper through-package-vias (TPVs), and copper traces in redistribution layer (RDL), on the thermal performance of glass interposers through numerical and experimental approaches. Numerical parametric study on 2.5D interposers shows that as more copper structures are incorporated in glass interposers, the performance of silicon and glass interposers becomes closer, showing 31% difference in thermal resistance, compared to 53% difference without any copper structures in both interposers. In the second part of this study, a thermal model of glass interposer mounted on the vapor chamber integrated PCB is developed using multi-scale modeling scheme. The comparison of thermal performance between silicon and glass interposers shows that integration of vapor chamber with PCB makes thermal performance of both interposers almost identical, overcoming the limitation posed by low thermal conductivity of glass. The third part of this thesis focuses on design, fabrication, and performance measurement of PCB integrated with vapor chamber. Copper micropillar wick structure is fabricated on PCB with electroplating process, and its wettability is enhanced by silica nanoparticle coating. Design of the wick for the vapor chamber is determined based on the capillary performance and permeability test results. Fabricated device with ultra-thin thickness (~800 µm) shows higher thermal performance than copper plated PCB with the same thickness. Finally, 3D computational fluid dynamics/heat transfer model of the vapor chamber is developed, and modeling result is compared with test result.Ph.D

Clock Network Design for 2.5D Heterogeneous Systems

The CMOS process technology scaling may have reached its pinnacle, yet not all ele- ments of computing can be manufactured at lower technological nodes. This has led to the development of a new branch of chip designing that allows chiplets on different technolog- ical nodes to be integrated on to a single package using interposers, the passive intercon- nection mediums. However, establishing a high-frequency communication over an entirely passive layer is one of the significant design challenges of 2.5D systems. My research will focus on building a robust clocking architecture for 2.5D systems, using a 64 core processor benchmark. The clocking scheme of any 2.5D design consists of two major components, viz., Interposer Clocking, and On-Chiplet Clocking. The interposer clocking consists of clocks used to achieve global synchronicity and clocks for inter-chiplet communication es- tablished using AIB protocol. These clocking components will be built using commercial EDA tools and analyzed using standard tools, and package/interconnect models. I will also be comparing these results against a 2D design of the same benchmark and against a differ- ent 2.5D clocking architecture to study if the 2.5D clock network can be designed to offer better power performance than the 2D counterpart.M.S

MICROELECTRONICS PACKAGING TECHNOLOGY ROADMAPS, ASSEMBLY RELIABILITY, AND PROGNOSTICS

This paper reviews the industry roadmaps on commercial-off-the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due tothe breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down-selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC). The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA). The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN), a data-driven PHM, was discussed in details. Finally, it presented inter- and extra-polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies

Design, Extraction, and Optimization Tool Flows and Methodologies for Homogeneous and Heterogeneous Multi-Chip 2.5D Systems

Chip and packaging industries are making significant progress in 2.5D design as a result of increasing popularity of their application. In advanced high-density 2.5D packages, package redistribution layers become similar to chip Back-End-of-Line routing layers, and the gap between them scales down with pin density improvement. Chiplet-package interactions become significant and severely affect system performance and reliability. Moreover, 2.5D integration offers opportunities to apply novel design techniques. The traditional die-by-die design approach neither carefully considers these interactions nor fully exploits the cross-boundary design opportunities. This thesis presents chiplet-package cross-boundary design, extraction, analysis, and optimization tool flows and methodologies for high-density 2.5D packaging technologies. A holistic flow is presented that can capture all parasitics from chiplets and the package and improve system performance through iterative optimizations. Several design techniques are demonstrated for agile development and quick turn-around time. To validate the flow in silicon, a chip was taped out and studied in TSMC 65nm technology. As the holistic flow cannot handle heterogeneous technologies, in-context flows are presented. Three different flavors of the in-context flow are presented, which offer trade-offs between scalability and accuracy in heterogeneous 2.5D system designs. Inductance is an inseparable part of a package design. A holistic flow is presented that takes package inductance into account in timing analysis and optimization steps. Custom CAD tools are developed to make these flows compatible with the industry standard tools and the foundry model. To prove the effectiveness of the flows several design cases of an ARM Cortex-M0 are implemented for comparitive study

Book of Knowledge (BOK) for NASA Electronic Packaging Roadmap

The objective of this document is to update the NASA roadmap on packaging technologies (initially released in 2007) and to present the current trends toward further reducing size and increasing functionality. Due to the breadth of work being performed in the area of microelectronics packaging, this report presents only a number of key packaging technologies detailed in three industry roadmaps for conventional microelectronics and a more recently introduced roadmap for organic and printed electronics applications. The topics for each category were down-selected by reviewing the 2012 reports of the International Technology Roadmap for Semiconductor (ITRS), the 2013 roadmap reports of the International Electronics Manufacturing Initiative (iNEMI), the 2013 roadmap of association connecting electronics industry (IPC), the Organic Printed Electronics Association (OE-A). The report also summarizes the results of numerous articles and websites specifically discussing the trends in microelectronics packaging technologies

Graphene Nanotechnology the Next Generation Logic, Memory and 3D Integrated Circuits

Title from PDF of title page viewed August 28, 2017Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 120-136)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2016Floating gate transistor is the basic building block of non-volatile flash memory, which is one of the most widely used memory gadgets in modern micro and nano electronic applications. Recently there has been a surge of interest to introduce a new generation of memory devices using graphene nanotechnology. In this paper we present a new floating gate transistor (FGT) design based on multilayer graphene nanoribbon (MLGNR) and carbon nanotube (CNT). In the proposed graphene based floating gate transistor (GFGT) a multilayer structure of graphene nanoribbon (GNR) would be used as the channel of the field effect transistor (FET) and a layer of CNTs would be used as the floating gate. We have performed an analysis of the charge accumulation mechanism in the floating gate and its dependence on the applied terminal voltages. Based on our analysis we have observed that proposed graphene based floating gate transistor could be operated at a reduced voltage compared to conventional silicon based floating gate devices. We have presented detail analysis of the operation and the programming and erasing processes of the proposed FGT, dependency of the programming and erasing current density on different parameters, impact of scaling the thicknesses of the control and tunneling oxides. These analyses are done based on the equivalent capacitance model of the device. We have analyze the programming and erasing by the tunneling current mechanism in the proposed graphene-CNT floating gate transistor. In this paper, we have investigated the mechanism of programming current and the factors that would influence this current and the behavior of the proposed floating gate transistor. The analysis reveals that programming is a strong function of the high field induced by the control gate, and the thicknesses of the control oxide and the tunnel oxide. With the growing demand for nonvolatile flash memory devices and increasing limitations of silicon technologies, there has been a growing interest to develop emerging flash memory by using alternative nanotechnology. The proposed FGT device for nonvolatile flash memory contains an MLGNR channel and a CNT floating gate with SiO₂ as the tunnel oxide. In this paper, we have presented detail analysis of the electrical properties and performance characteristics of the proposed FGT device. We have focused on the following aspects: current voltage (I-V) characteristics, threshold voltage variation (∆VTH), programming, erasing and reading power consumptions compared to the existing FGTs, and layer-by-layer current voltage characteristics comparison of the proposed GFGT device. To realize graphene field effect transistor (GFET), a general model is developed, validated and analyzed. This model is also used to estimate graphene channel behavior of the proposed GFGT. Reliability is the major concern of the Flash memory technology. We have analyzed retention characteristics of the proposed GFGT. We also have developed a radiation harness test model for the Si-FGT by using VTH variation principle due to the radiation exposure. Flash memory experiences adverse effects due to radiation. These effects can be raised in terms of doping, feature size, supply voltages, layout, shielding. The operating point shift of the device forced to enter the logically-undefined region and cause upset and data errors under radiation exposure. In this research, the threshold voltage shift of the floating gate transistor (FGT) is analyzed by a mathematical model. Molybdenum disulfide (MoS2) based field effect transistor is considered as one of the promising future logic devices. Many other nanoelectronic devices based on MoS2 are currently under investigation. However, the challenge of providing reliable and efficient contact between 2D materials like MoS2 and the metal is still unresolved. The contact resistance between metal and MoS2 limits the application of MoS2 in current semiconductor technologies. In this paper, a detail analysis of metal-MoS2 contact has been presented. Specific contributions of this work are:investigation of the physical, material and electrical parameters that would determine the contact properties, analysis of the combined impact of the top and back gates for the first time, modeling of the crucial metal-MoS2 contact parameters, such as, sheet resistance (RSh), contact resistivity (ρc), contact resistance (RC) and transfer length (LT), investigation of the ways to incorporate the developed contact model into the electronic design automation (EDA) tools and investigation of different contact materials for the metal-MoS2 contact. The three dimensional integrated circuit (3D- IC) is expected to extend Moore's law. To reduce interconnects and time delay, semiconductor industry is shifting 2D-IC to 2.5D-IC and 3D-IC. 3D-IC is the ultimate goal of the semiconductor industry, where 2.5D-IC is an intermediate state. It is important to realize CAD design challenges of the 2.5D-IC/3D-IC when minimum spacing interconnects are used. The major contributions of this research work are as follows. Previously, for the small scale experimental purpose, small numbers (10-20) of TSVs, interconnects, bumps are fabricated together by hand calculation. However in the real 3D-IC design, thousands of TSVs, interconnects, bumps are reuired. Therefore, an automated CAD solution is required to provide precise physical design and verification. Therefore, a solid CAD solution is provided here. Compatible with 40nm-technology design, which enables the Silicon Interposer to integrate with the digital, analog and RF dies together. Dimensions and spacing of the TSV and Bump are optimized by the 3D EM full wave field solver. To our best knowledge, at the interposer level, this design reports the most dense and well-defined RDL, TSV and micro-bump co-design on Silicon Interposer, which will be used for 2.5D-IC.Introduction and background -- Proposed Graphene Based Flash Memory -- Physical and Electrical Parameters of the Proposed Graphene Flash Memory Device -- Programming and Erasing Operation of the Proposed Graphene Flash Memory Device -- Reliability Analysis of the Proposed Graphene Flash Memory Device -- Radiation Hardness Analysis of the Floating Gate Transistor -- Benchmarking of the Proposed Graphene Flash Memory Device -- Graphene Field Effect Transistor (GFET) Generalized Model -- MoS2 FET Device and Contact Characterization and Modelling based on Modified Transfer Length Method (TLM) -- 2.5D Silicon Interposer Design in 40nm-Technology for 2D-IC and 3D-IC -- Conclusion and Future Wor

Development of Silicon Photonic Multi Chip Module Transceivers

The exponential growth of data generation–driven in part by the proliferation of applications such as high definition streaming, artificial intelligence, and the internet of things–presents an impending bottleneck for electrical interconnects to fulfill data center bandwidth demands. Links now require bandwidths in excess of multiple Tbps while operating on the order of picojoules per bit, in addition to constraints on areal bandwidth densities and pin I/O bandwidth densities. Optical communications built on a silicon photonic platform offers a potential solution to develop power efficient, high bandwidth, low attenuation, small footprint links, all while building off the mature CMOS ecosystem. The development of silicon photonic foundries supporting multi project wafer runs with associated process design kit components supports a path towards widespread commercial production by increasing production volume while reducing fabrication and development costs. While silicon photonics can always be improved in terms of performance and yield, one of the central challenges is the integration of the silicon photonic integrated circuits with the driving electronic integrated circuits and data generating compute nodes such as CPUs, FPGAs, and ASICs. The co-packaging of the photonics with the electronics is crucial for adoption of silicon photonics in datacenters, as improper integration negates all the potential benefits of silicon photonics. The work in this dissertation is centered around the development of silicon photonic multi chip module transceivers to aid in the deployment of silicon photonics within data centers. Section one focuses on silicon photonic integration and highlights multiple integrated transceiver prototypes. The central prototype features a photonic integrated circuit with bus waveguides with WDM microdisk modulators for the transmitter and WDM demuxes with drop ports to photodiodes for the receiver. The 2.5D integrated prototype utilizes a thinned silicon interposer and TIA electronic integrated circuits. The architecture, integration, characterization, performance, and scalability of the prototype are discussed. The development of this first prototype identified key design considerations necessary for designing multi chip module silicon photonic prototypes, which will be addressed in this section. Finally, other multi chip module silicon photonic prototypes will be overviewed. These include a 2.5D integrated transceiver with a different electronic integrated circuit TIA, a 3D integrated receiver, an active interposer network on chip, and a 2.5D integrated transceiver with custom electronic integrated circuits. Section two focuses on research that supports the development of silicon photonic transceivers. The thermal crosstalk from neighboring microdisk modulators as a function of modulator pitch is investigated. As modulators are placed at denser pitches to accommodate areal bandwidth density requirements in transceivers, this thermal crosstalk will become significant. In this section, designs and results from several iterations of custom microring modulators are reported. Custom microring modulators allow for scaling up the number of channels in microring transceivers by offering the ability to fabricate variable resonances and provide a platform for further innovation in bandwidth, free spectral range, and energy efficiency. The designs and results of higher order modulation format modulators, both microring based and Mach Zehnder based, are discussed. High order modulators offer a path towards scaling transceiver total throughput without having to increase the channel counts or component bandwidth. Together, the work in these two sections supports the development of silicon photonic transceivers to aid in the adoption of silicon photonics into data generating systems