Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS

In questo lavoro si presenta una metodologia di progettazione elettronica a livello di sistema, affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di equazioni atti a selezionare le configurazione di interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre, il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso

Space-Compliant Design of a Millimeter-Wave GaN-on-Si Stacked Power Amplifier Cell through Electro-Magnetic and Thermal Simulations

The stacked power amplifier is a widely adopted solution in CMOS technology to overcome breakdown limits. Its application to compound semiconductor technology is instead rather limited especially at very high frequency, where device parasitic reactances make the design extremely challenging, and in gallium nitride technology, which already offers high breakdown voltages. Indeed, the stacked topology can also be advantageous in such scenarios as it can enhance gain and chip compactness. Moreover, the higher supply voltages and lower supply currents beneficially impact on reliability, thus making the stacked configuration an attractive solution for space applications. This paper details the design of two stacked cells, differing in their inter-stage matching strategy, conceived for space applications at Ka-band in 100 nm GaN-on-Si technology. In particular, the design challenges related to the thermal constraints posed by space reliability and to the electro-magnetic cross-talk issues that may arise at millimeter-wave frequencies are discussed. The best cell achieves at saturation, in simulation, 3 W of output power at 36 GHz with associated gain and efficiency in excess of 7 dB and 35%, respectively

Ultra Wideband 5 W Hybrid Power Amplifier Design Using Silicon Carbide MESFETs

Aufgrund des hohen Bandabstandes von SiC besitzen SiC-MESFETs ein hohe Duruchbruchspannung und können folglich bei hohen Versorgungsspannungen betrieben werden. Darüber hinaus besitzen sie eine hohe Elektronensätigungsgeschwindigkeit und Wärmeleitfähigkeit. Aufgrund diese eigenschaften eignen sich diese bauelemente hervorragend für die Entwiklung von breitbandigen Leistungsverstärkern bis in den unteren GHz-Bereich. In dieser Arbeit wird ein neues empirisches Modell für SiC MESFET vorgeschlagen. Ein kommerziell erhältlicher, gehäuster MESFET Typ (CREE CRF24010) wird für die Entwicklung des Modelles verwendet. Messungen wurden sowohl in Arbeitspunkten mit als auch ohne Vorspannung durchgeführt um die Gleichungen und Parameter abzuleiten. Die Cold FET Technik wurde verwendet um die parasitären extrinsischen Elemente zu bestimmen, während die arbeitspunktabhängigen Elemente des Modelles analytisch bei mehreren Arbeitspunkten bestimmt wurden. Nichtlineare Gleichungen für die arbeitspunktabhängigen Elemente wurden ebenfalls abgeleitet. Das so entwickelte Modell für den SiC MESFET wurde sowohl hinsichtlich des Kleinsignal als auch des Großsignalverhaltens überprüft. Fünf verschiedene Generationen von Breitband-Leistungsverstärkern wurden auf Grundlage des entwickelten Modelles implementiert. Dabei wurde keinerlei Impedanztransformator eingesetzt. Eine neuartige breitbandige Biasstruktur wurde entwickelt, um gute Isolation und geringe Verluste über die angestrebte Bandbreite zu erreichen. Die Anpassungsnetzwerke an Eingang, Ausgang und zwischen den Stufen sowie die Parallel-Rückkopplung wurden mit Hilfe von Mikrostreifenleitungstechnik realisiert um die Bandbreite zu erhöhen und die Stabilität zu verbessern. Als erste Generation wird ein einstufiger 5 Watt Leistungsverstärker mit einem SiC MESFET entworfen und aufgebaut, der den Frequenzbereich von 10 MHz bis 2,4 GHz abdeckt. Eine Leistungsverstärkung von 6 dB, 37 dBm Ausgangsleistung, 33% PAE und 52 dBm OIP3 wurden erreicht. Ein zweistufiger Leistungsverstärker mit hoher Verstärkung für die selbe Bandbreite, der einen GaAs und einen SiC MESFET in Kaskade verwendet, wurde ebenfalls aufgebaut. Typische Werte von 23 dB Leistungsverstärkung, 37 dBm Ausgangsleistung, 28 % PAE und 47 dBm OIP3 wurden erreicht. Der Einfluss der Treiberstufe auf die Leistungs- und Linearitätseigenschaften der zweiten Generation wurde untersucht. Basierend auf SiC Chips wurden die dritte und vierte Generation in Form von einstufigen und zweistufigen ultra-breitband Leistungsverstärkern implementiert, die das Frequenzband von 1 MHz bis 5 GHz abdecken. Der Einfluss des GaAs FET Treibers in der vierten Kategorie auf die Gesamteigenschaften wurde ebenfalls diskutiert. Unter Einsatz der Rückkopplungs-Kompensationstechnik wurde ein schmalbandiger 10 W Leistungsverstärkerentwurf mit hoher Verstärkung, basierend auf einem SiC Chip, als fünftes Beispiel vorgestellt. Alle Leistungs- und Linearitäts-Ergebnisse wurden über das gesamte Frequenzband ermittelt. Die Entwurfsprozedur wird detailliert beschrieben und die Ergebnisse werden diskutiert und ausführlich mit den Simulationen verglichen.SiC MESFETs have an enormous potential for realizing high-power amplifiers at microwave frequencies due to their wide band-gap features of high breakdown field, high electron saturation velocity and high operating temperature. In this thesis, a new empirical model for SiC MESFET is proposed. A commercially packaged high power MESFET device (CREE CRF24010) is adopted for the model development. Both hot and cold bias condition measurements are performed to derive equations and parameters. Cold FET technique is used to extract the parasitic extrinsic elements whereas the bias-dependent model elements are extracted analytically from multiple bias points. Nonlinear equations for the bias dependent elements are derived, too. The derived model for the SiC MESFET has been verified in small signal as well as large signal performances. Five different generations of broadband power amplifiers based on the developed model have been implemented. No impedance transformer was used at all. A novel broadband choke structure has been developed to obtain good isolation and low loss over the desired bandwidth. Input, interstage and output matching networks and shunt feedback topology have been designed based on microstip technique to increase the bandwidth and improve the stability. In the first generation, a single stage 5-watt power amplifier using a SiC MESFET covering the frequency range from 10 MHz to 2.4 GHz is designed and fabricated. A power gain of 6 dB, 37 dBm output power, 33 % PAE and 52 dBm OIP3 have been achieved. A high gain two stage power amplifier covering the same bandwidth using a GaAs- and a SiC- MESFET in cascade also has been fabricated. Typical values of 23 dB power gain, 37 dBm output power, 28 % PAE and 47 dBm OIP3 have been obtained. The impact of the driver stage on power and linearity performances of the second generation has been discussed. Based on SiC Chip, the third and the fourth generation represent ultra wideband single stage and two stage power amplifiers, covering the frequency band from 1 MHz to 5 GHz have been simulated. Small signal and harmonic balance simulations based on ADS have been introduced. The impact of the GaAs FET driver in the fourth category on the overall performances also has been discussed. Using feedback compensation technique, a 10-W narrow band high gain power amplifier design based on SiC Chip has been presented as a fifth example. All power and linearity results were obtained over the whole frequency band. The design procedure is given in detail and the results are being discussed and compared with simulations extensively

올 디지털 클럭 및 데이터 복원 회로를 적용한 고속 광 수신기 설계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 정덕균.This thesis presents a 22- to 26.5-Gb/s optical receiver with an all-digital clock and data recovery (ADCDR) fabricated in a 65-nm CMOS process. The receiver consists of an optical front-end and a half-rate bang-bang clock and data recovery circuit. The optical front-end achieves low power consumption by using inverter-based amplifiers and realizes sufficient bandwidth by applying several bandwidth extension techniques. In addition, in order to minimize additional jitter at the front-end, not only magnitude and bandwidth but also phase delay responses are considered. The ADCDR employs an LC quadrature digitally-controlled oscillator (LC-QDCO) to achieve a high phase noise figure-of-merit at tens of gigahertz. The recovered clock jitter is 1.28 psrms and the measured jitter tolerance exceeds the tolerance mask specified in IEEE 802.3ba. The receiver sensitivity is 106 and 184 μApk-pk for a bit error rate of 10−12 at data rates of 25 and 26.5 Gb/s, respectively. The entire receiver chip occupies an active die area of 0.75 mm2 and consumes 254 mW at a data rate of 26.5 Gb/s. The energy efficiencies of the front-end and entire receiver at 26.5 Gb/s are 1.35 and 9.58 pJ/bit, respectively.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 5 CHAPTER 2 DESIGN OF OPTICAL FRONT-END 7 2.1 OVERVIEW 7 2.2 BACKGROUND ON OPTICAL FRONT-END 9 2.2.1 PHOTODIODE 9 2.2.2 TRANSIMPEDANCE AMPLIFIER 11 2.2.3 POST AMPLIFIER 17 2.2.4 SHUNT INDUCTIVE PEAKING 25 2.3 CIRCUIT IMPLEMENTATION 29 2.3.1 OVERALL ARCHITECTURE 29 2.3.2 TRANSIMPEDANCE AMPLIFIER 31 2.3.3 POST AMPLIFIER 34 2.4 NOISE ANALYSIS 43 2.4.1 PHOTODIODE 43 2.4.2 OPTICAL FRONT-END 44 2.4.3 SENSITIVITY 46 CHAPTER 3 DESIGN OF ADCDR FOR OPTICAL RECEIVER 48 3.1 OVERVIEW 48 3.2 BACKGROUND ON PLL-BASED ADCDR 51 3.2.1 PHASE DETECTOR 51 3.2.2 DIGITAL LOOP FILTER 54 3.2.3 DIGITALLY-CONTROLLED OSCILLATOR 56 3.2.4 ANALYSIS OF BANG-BANG ADCDR 67 3.3 CIRCUIT IMPLEMENTATION 70 3.3.1 OVERALL ARCHITECTURE 70 3.3.2 PHASE DETECTION LOGIC 75 3.3.3 DIGITAL LOOP FILTER 77 3.3.4 LC QUADRATURE DCO 78 CHAPTER 4 EXPERIMENTAL RESULTS 82 CHAPTER 5 CONCLUSION 90 BIBLIOGRAPHY 92 초록 101Docto

Fully integrated CMOS power amplifier design using the distributed active-transformer architecture

A novel on-chip impedance matching and power-combining method, the distributed active transformer is presented. It combines several low-voltage push-pull amplifiers efficiently with their outputs in series to produce a larger output power while maintaining a 50-Ω match. It also uses virtual ac grounds and magnetic couplings extensively to eliminate the need for any off-chip component, such as tuned bonding wires or external inductors. Furthermore, it desensitizes the operation of the amplifier to the inductance of bonding wires making the design more reproducible. To demonstrate the feasibility of this concept, a 2.4-GHz 2-W 2-V truly fully integrated power amplifier with 50-Ω input and output matching has been fabricated using 0.35-μm CMOS transistors. It achieves a power added efficiency (PAE) of 41 % at this power level. It can also produce 450 mW using a 1-V supply. Harmonic suppression is 64 dBc or better. This new topology makes possible a truly fully integrated watt-level gigahertz range low-voltage CMOS power amplifier for the first time

Amplifiers with prescribed frequency characteristics and arbitrary bandwidth

"July 7, 1950."Bibliography: p. 61.Army Signal Corps Contract No. W36-039-sc-32037 Project No. 102B Dept. of the Army Project No. 3-99-10-022John G. Linvill

Design of broadband inductor-less RF front-ends with high dynamic range for G.hn

System-on-Chip (SoC) was adopted in recent years as one of the solutions to reduce the cost of integrated systems. When the SoC solution started to be used, the final product was actually more expensive due to lower yield. The developments in integrated technology through the years allowed the integration of more components in lesser area with a better yield. Thus, SoCs became a widely used solution to reduced the cost of the final product, integrating into a single-chip the main parts of a system: analog, digital and memory. As integrated technology kept scaling down to allow a higher density of transistors and thus providing more functionality with the same die area, the analog RF parts of the SoC became a bottleneck to cost reduction as inductors occupy a large die area and do not scale down with technology. Hence, the trend moves toward the research and design of inductor-less SoCs that further reduce the cost of the final solution. Also, as the demand for home networking high-data-rates communication systems has increased over the last decade, several standards have been developed to satisfy the requirements of each application, the most popular being wireless local area networks (WLANs) based on the IEEE 802.11 standard. However, poor signal propagation across walls make WLANs unsuitable for high-speed applications such as high-definition in-home video streaming, leading to the development of wired technologies using the existing in-home infrastructure. The ITU-T G.hn recommendation (G.9960 and G.9961) unifies the most widely used wired infrastructures at home (coaxial cables, phone lines and power lines) into a single standard for high-speed data transmission of up to 1 Gb/s. The G.hn recommendation defines a unified networking over power lines, phone lines and coaxial cables with different plans for baseband and RF. The RF-coax bandplan, where this thesis is focused, uses 50 MHz and 100 MHz bandwidth channels with 256 and 512 carriers respectively. The center frequency can range from 350 MHz to 2450 MHz. The recommendation specifies a transmission power limit of 5 dBm for the 50 MHz bandplan and 8~dBm for the 100 MHz bandplan, therefore the maximum transmitted power in each carrier is the same for both bandplans. Due to the nature of an in-home wired environment, receivers that can handle both very large and very small amplitude signals are required; when transmitter and receiver are connected on the same electric outlet there is no channel attenuation and the signal-to-noise-plus-distortion ratio (SNDR) is dominated by the receiver linearity, whereas when transmitter and receiver are several rooms apart channel attenuation is high and the SNDR is dominated by the receiver noise figure. The high dynamic range specifications for these receivers require the use of configurable-gain topologies that can provide both high-linearity and low-noise for different configurations. Thus, this thesis has been aimed at researching high dynamic range broadband inductor-less topologies to be used as the RF front-end for a G.hn receiver complying with the provided specifications. A large part of the thesis has been focused on the design of the input amplifier of the front-end, which is the most critical stage as the noise figure and linearity of the input amplifier define the achievable overall specifications of the whole front-end. Three prototypes has been manufactured using a 65 nm CMOS process: two input RFPGAs and one front-end using the second RFPGA prototype.El "sistema en un chip" (SoC) fue adoptado recientemente como una de las soluciones para reducir el coste de sistemas integrados. Cuando se empezó a utilizar la solución SoC, el producto final era más caro debido al bajo rendimiento de producción. Los avances en tecnología integrada a lo largo de los años han permitido la integración de más componentes en menos área con mejoras en rendimiento. Por lo tanto, SoCs pasó a ser una solución ampliamente utilizada para reducir el coste del producto final, integrando en un único chip las principales partes de un sistema: analógica, digital y memoria. A medida que las tecnologías integradas se reducían en tamaño para permitir una mayor densisdad de transistores y proveer mayor funcionalidad con la misma área, las partes RF analógicas del SoC pasaron a ser la limitación en la reducción de costes ya que los inductores ocupan mucha área y no escalan con la tecnología. Por lo tanto, las tendencias en investigación se mueven hacia el diseño de SoCs sin inductores que todavía reducen más el coste final del producto. También, a medida que la demanda en sistemas de comunicación domésticos de alta velocidad ha crecido a lo largo de la última década, se han desarrollado varios estándares para satisfacer los requisitos de cada aplicación, siendo las redes sin hilos (WLANs) basadas en el estándar IEEE 802.11 las más populares. Sin embargo, una pobre propagación de señal a través de las paredes hacen que las WLANs sean inadecuadas para aplicaciones de alta-velocidad como transmisión de vídeo de alta definición en tiempo real, resultando en el desarrollo de tecnologías con hilos utilizando la infraestructura existente en los domicilios. La recomendación ITU-T G.hn (G.9960 and G.9961) unifica las principales infraestructuras con hilos domésticas (cables coaxiales, línias de teléfono y línias de electricidad) en un sólo estándar para la transmisión de datos hasta 1 Gb/s. La recomendación G.hn define una red unificada sobre línias de electricidad, de teléfono y coaxiales con diferentes esquemas para banda base y RF. El esquema RF-coax en el cual se basa esta tesis, usa canales con un ancho de banda de 50 MHz y 100 MHz con 256 y 512 portadoras respectivamente. La frecuencia centra puede variar desde 350 MHz hasta 2450 MHz. La recomendación especifica un límite en la potencia de transmisión de 5 dBm para el esquema de 50 MHz y 8 dBm para el esquema de 100 MHz, de tal forma que la potencia máxima por portadora es la misma en ambos esquemas. Debido a la estructura de un entorno doméstico con hilos, los receptores deben ser capaces de procesar señales con amplitud muy grande o muy pequeña; cuando transmisor y receptor están conectados en la misma toma eléctrica no hay atenuación de canal y el ratio de señal a rudio más distorsión (SNDR) está dominado por la linealidad del receptor, mientras que cuando transmisor y receptor están separados por varias habitaciones la atenuación es elevada y el SNDR está dominado por la figura de ruido del receptor. Los elevados requisitos de rango dinámico para este tipo de receptores requieren el uso de topologías de ganancia configurable que pueden proporcionar tanto alta linealidad como bajo ruido para diferentes configuraciones. Por lo tanto, esta tesis está encarada a la investigación de topologías sin inductores de banda ancha y elevado rango dinámico para ser usadas a la entrada de un receptor G.hn cumpliendo con las especificaciones proporcionadas. Una gran parte de la tesis se ha centrado en el diseño del amplificador de entrada al ser la etapa más crítica, ya que la figura de ruido y linealidad del amplificador de entrada definen lás máximas especificaciones que el sistema puede conseguir. Se han fabricado 3 prototipos con un proceso CMOS de 65 nm: 2 amplificadores y un sistema completo con amplificador y mezclador.Postprint (published version