A novel low-voltage reconfigurable ΣΔ modulator for 4G wireless receivers

This paper presents a new adaptable cascade ΣΔ modulator architecture fo r low-voltage multi-stan- dard applications. It uses two reconfiguration strategies: a programmable global resonation and a variable loop-filter order. These techniques are properly com- bined in a novel topology that allows to increase the effec- tive resolution in a given bandwidth, whereas keeping relaxed output swing requirements and high robustness to mismatch and to non-linearities of the amplifiers. Time-domain simulations incl uding the main circuit-level non-idealities are shown to demonstrate the benefits of the presented modulator when it is configured to cope with the requirements of GSM, UMTS, WLAN and Wi-Max.España, Ministerio de Educación y Ciencia TEC2007-67247-C02-01/MICEspaña, Ministerio de Innovación, Ciencia y Empresa, Junta de Andalucía TIC-253

Evaluation of Sigma-Delta-over-Fiber for High-Speed Wireless Applications

Future mobile communication networks aim to increase the communication speed,\ua0provide better reliability and improve the coverage. It needs to achieve all of these enhancements, while the number of users are increasing drastically. As a result, new base-station (BS) architectures where the signal processing is centralized and wireless access is provided through multiple, carefully coordinated remote radio heads are needed. Sigma-delta-over-fiber (SDoF) is a communication technique that can address both requirements and enable very low-complexity, phase coherent remote radio transmission, while transmitting wide-band communication signals with high quality. This thesis investigates the potential and limitations of SDoF communication links as an enabler for future mobile networks.In the first part of the thesis, an ultra-high-speed SDoF link is realized by using state-of-the-art vertical-cavity surface-emitting-lasers (VCSEL). The effects of VCSEL characteristics on such links in terms of signal quality, energy efficiency and potential lifespan is investigated. Furthermore, the potential and limitations of UHS-SDoF are evaluated with signals having various parameters. The results show that, low-cost, reliable, energy efficient, high signal quality SDoF links can be formed by using emerging VCSEL technology. Therefore, ultra-high-speed SDoF is a very promising technique for beyond 10~GHz communication systems.In the second part of the thesis, a multiple-input-multiple-output (MIMO) communication testbed with physically separated antenna elements, distributed-MIMO, is formed by multiple SDoF links. It is shown that the digital up-conversion, performed with a shared local-oscillator/clock at the central unit, provides excellent phase coherency between the physically distributed antenna elements. The proposed testbed demonstrates the advantages of SDoF for realizing distributed MIMO systems and is a powerful tool to perform various communication experiments in real environments.In general, SDoF is a solution for the downlink of a communication system, i.e. from central unit to remote radio head, however, the low complexity and low cost requirement of the remote radio heads makes it difficult to realize the uplinks of such systems. The third part of this thesis proposes an all-digital solution for realizing complementary uplinks for SDoF systems. The proposed structure is extensively investigated through simulations and measurements and the results demonstrate that it is possible realize all-digital, duplex, optical communication links between central units and remote radio heads.In summary, the results in this thesis demonstrate the potential of SDoF for wideband, distributed MIMO communication systems and proposes a new architecture for all-digital duplex communication links. Overall, the thesis shows that SDoF technique is powerful technique for emerging and future mobile communication networks, since it enables a centralized structure with low complexity remote radio heads and provides high signal quality

Radio-Communications Architectures

Wireless communications, i.e. radio-communications, are widely used for our different daily needs. Examples are numerous and standard names like BLUETOOTH, WiFI, WiMAX, UMTS, GSM and, more recently, LTE are well-known [Baudoin et al. 2007]. General applications in the RFID or UWB contexts are the subject of many papers. This chapter presents radio-frequency (RF) communication systems architecture for mobile, wireless local area networks (WLAN) and connectivity terminals. An important aspect of today's applications is the data rate increase, especially in connectivity standards like WiFI and WiMAX, because the user demands high Quality of Service (QoS). To increase the data rate we tend to use wideband or multi-standard architecture. The concept of software radio includes a self-reconfigurable radio link and is described here on its RF aspects. The term multi-radio is preferred. This chapter focuses on the transmitter, yet some considerations about the receiver are given. An important aspect of the architecture is that a transceiver is built with respect to the radio-communications signals. We classify them in section 2 by differentiating Continuous Wave (CW) and Impulse Radio (IR) systems. Section 3 is the technical background one has to consider for actual applications. Section 4 summarizes state-of-the-art high data rate architectures and the latest research in multi-radio systems. In section 5, IR architectures for Ultra Wide Band (UWB) systems complete this overview; we will also underline the coexistence and compatibility challenges between CW and IR systems

Efficient Design and Synthesis of Decimation Filters for Wideband Delta-Sigma ADCs

A design methodology for synthesizing power-optimized decimation filters for wideband Delta Sigma (ΔΣ) analog-to-digital converters (ADCs) for next-generation wireless standards is presented. The decimation filter is designed to filter the out-of-band quantization noise from a fifth-order continuous-time ΔΣ modulator, with 20 MHz signal bandwidth and 14-bits resolution. The modulator employs an oversampling ratio (OSR) of 16 with a clock rate of 640 MHz. Retiming, pipelining, Canonical Signed Digits (CSD) encoding has been utilized along with an optimized halfband filter to realize the power savings in the overall decimation filter. A process flow to rapidly design the optimized filters in MATLAB, generate the hardware description language (HDL) code and then automatically synthesize the design using standard cells has been presented. The decimation filter is implemented using standard cells in a 45 nm CMOS technology occupies a layout area of 0.12 mm2 and consumes 8 mW power from the 1.1 V supply

Modeling a IF double sampling bandpass switched capacitor ΣΔ ADC with a symmetric noise transfer function for WiMAX/WLAN

4G technology aims to revolutionize private and professional communication with its ubiquity and high-speed transmission (averaging 100Mbps). WiMAX and WLAN are two of the high speed access technologies to be used in the 4G mobile communication. Apropos to their high bandwidths, oversampling converters, e.g.ΣΔ ADCs, used for these standards would entail high levels of power consumption. Double sampling technique used in ΣΔ ADCs help in reducing the power consumption, since the actual sampling rate is only half the sampling frequency required to achieve a target resolution. But for conventional modulators, with low pass noise transfer functions (NTF), this benefit is hampered by the introduction of folded noise due to the mismatch of sampling capacitances. This paper presents a novel method of designing IF bandpass switched capacitor (SC)ΣΔ modulators with symmetric NTFs. Such a bandpass NTF is formulated with its center frequency at one-fourth the effective sampling frequency. The symmetricity ensures that the folded noise is `noise-shaped' along with the quantization noise. The idea is verified with a discrete time bandpass ΣΔ modulator modeled using Simulink®, including various nonlinearities, viz. clock jitter, opampnonidealities, and capacitive mismatch effects owing to double sampling and use of a multibitquantizer. Behavioral simulations of the proposed non-ideal model for WiMAX and WLAN, with a bandwith of 10MHz and 11MHz, respectively, achieved a peak resolution greater than 10 bits for each of the standards

A 10-b Fourth-Order Quadrature Bandpass Continuous-Time ΣΔ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

This document is the Accepted Manuscript version of the following article: Junfeng Zhang, Yang Xu, Zehong Zhang, Yichuang Sun, Zhihua Wang, and Baoyong Chi, ‘A 10-b Fourth-Order Quadrature Bandpass Continuous-Time ΣΔ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver’, IEEE Transactions on Microwave Theory and Practice, Vol. 65 (4): 1303-1314, first published online 16 February 2017. The version of record is available online at DOI: 10.1109/TMTT.2017.266237, Published by IEEE. © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.A fourth-order quadrature bandpass continuous-time sigma-delta modulator for a dual-channel global navigation satellite system (GNSS) receiver is presented. With a bandwidth (BW) of 33 MHz, the modulator is able to digitalize the downconverted GNSS signals in two adjacent signal bands simultaneously, realizing dual-channel GNSS reception with one receiver channel instead of two independent receiver channels. To maintain the loop-stability of the high-order architecture, any extra loop phase shifting should be minimized. In the system architecture, a feedback and feedforward hybrid architecture is used to implement the fourth-order loop-filter, and a return-to-zero (RZ) feedback after the discrete-time differential operation is introduced into the input of the final integrator to realize the excess loop delay compensation, saving a spare summing amplifier. In the circuit implementation, power-efficient amplifiers with high-frequency active feedforward and antipole-splitting techniques are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-b quantizers. These power saving techniques help achieve superior figure of merit for the presented modulator. With a sampling rate of 460 MHz, current-steering digital-analog converters are chosen to guarantee high conversion speed. Implemented in only 180-nm CMOS, the modulator achieves 62.1-dB peak signal to noise and distortion ratio, 64-dB dynamic range, and 59.3-dB image rejection ratio, with a BW of 33 MHz, and consumes 54.4 mW from a 1.8 V power supply.Peer reviewe