This paper presents a new adaptable cascade
ΣΔ
 modulator architecture fo
r low-voltage multi-stan-
dard applications. It uses two reconfiguration strategies:
a programmable global resonation and a variable
loop-filter order. These techniques are properly com-
bined in a novel topology that allows to increase the effec-
tive resolution in a given bandwidth, whereas keeping
relaxed output swing requirements and high robustness
to mismatch and to non-linearities of the amplifiers.
Time-domain simulations incl
uding the main
 circuit-level
non-idealities are shown to demonstrate the benefits of
the presented modulator when it is configured to cope
with the requirements of GSM, UMTS, WLAN and
Wi-Max.España, Ministerio de Educación y Ciencia TEC2007-67247-C02-01/MICEspaña, Ministerio de Innovación, Ciencia y Empresa, Junta de Andalucía TIC-253

Morgado García de la Polavieja, Alonso

Rosa Utrera, José Manuel de la

Río Fernández, Rocío del

English

idUS. Depósito de Investigación Universidad de Sevilla

Abstract − This paper presents a new adaptable cascadeΣΔ modulator architecture for low-voltage multi-stan-dard applications. It uses two reconfiguration strategies:a programmable global resonation and a variableloop-filter order. These techniques are properly com-bined in a novel topology that allows to increase the effec-tive resolution in a given bandwidth, whereas keepingrelaxed output swing requirements and high robustnessto mismatch and to non-linearities of the amplifiers.Time-domain simulations including the main circuit-levelnon-idealities are shown to demonstrate the benefits ofthe presented modulator when it is configured to copewith the requirements of GSM, UMTS, WLAN andWi-Max.†I. INTRODUCTIONSigma-Delta Modulators (ΣΔMs) are very suitedfor the implementation of reconfigurable Ana-log-to-Digital Converters (ADCs) required for thefourth generation (4G or Beyond-3G) of wirelesshand-held devices [1]. Based on the combined use ofoversampling and noise shaping, ΣΔMs can adapt theirdynamic ranges to different specifications with largehardware re-use, reduced power consumption and atthe lowest cost [2]-[9].Although changing the sampling frequency hasbeen the reconfiguration strategy most commonlyapplied, the mandatory use of low OverSamplingRatios (OSRs) in wideband communication standardshas forced ΣΔMs to achieve the required dynamicranges by resorting to different strategies, including:high-order shaping [2][6][8][9], switchable cascadetopologies [5][9]; programmable notches within thesignal band [2][8]; and multi-bit embedded quantizers[3][7][9]. However, the efficient implementation ofthese techniques requires to explore new ΣΔM topolo-gies capable of adapting their performance to as manyspecifications as possible while keeping high robust-ness to circuit errors.The modulator presented in this paper is based onthree strategies to adapt its functionality to differentspecifications. First, the modulator loop-filter ordercan be varied according to the required performance byconnecting or disconnecting low-order stages in a cas-cade topology. Second, resonation is used to optimallydistribute the zeroes of the Noise Transfer Function(NTF) within the required signal bandwidth. Third, aunity Signal Transfer Function (STF) is employed inall stages of the cascade for reducing the amplifier out-put swing requirements [10]. The above-mentionedstrategies are combined in a novel reconfigurable cas-cade ΣΔM topology that maximizes the effective reso-lution within a given bandwidth with reduced circuitcomplexity, low sensitivity to element mismatches andhigh robustness with respect to opamp non-linearities.II. PROPOSED MODULATORFig.1 shows the proposed modulator architecture.It consists of a reconfigurable cascade topology thatmakes use of two concepts, namely: unity STF [10]and global resonation [11]. The former is implementedby the feedforward paths that connect the input of eachstage with the corresponding quantizer inputs, whereasglobal resonation is achieved thanks to the inter-stagepaths (highlighted in Fig.1) that feed back a delayedscaled version of the last-stage quantization error at theinput of the first-stage quantizer. One important advan-tage of the proposed modulator is that, on the contraryto the one reported in [11], only Forward-Euler (FE)†. This work has been supported by the Spanish Ministry of Scienceand Education (with support from the European Regional Devel-opment Fund) under contract TEC2007-67247-C02-01/MIC andthe Andalusian (Regional) Ministry of Innovation, Science andEnterprise under contract TIC-2532.+ Fig. 1: Proposed reconfigurable ΣΔM topology.-+ Σ + +2-+ Σ H z( ) Σ++ +21 d⁄+ Σ-Σ+Σ +1 z 1––( )2-x yB1+dH z( )H z( ) H z( ) B2K d⁄ K d⁄SrSrSrSrSLH z( ) z1–1 z 1––----------------=SL SLA Novel Low-Voltage ReconfigurableΣΔ Modulator for 4G Wireless ReceiversAlonso Morgado, Rocío del Río and José M. de la RosaInstitute of Microelectronics of Seville (IMSE-CNM, CSIC) and Universidad de SevillaEdif. CICA-CNM, Avda. Reina Mercedes s/n, 41012- Sevilla, SPAINPhone: +34 95 5056666, Fax: +34 95 5056686, E-mail: {alonso|rocio|jrosa}@imse.cnm.esintegrators are required, thus making itsSwitched-Capacitor (SC) implementation easier.The modulator includes a number of switches toconfigure the NTF according to the required perfor-mance. On the one hand, by connecting the switchableerror feedback paths from the last to the first stage—with switches  and  in ON mode— the globalresonation scheme is enabled. On the other hand, theorder of the cascade is also reconfigurable. Both recon-figuration strategies (adaptive global resonation andNTF order) can be used independently, thus givingmore flexibility to the ΣΔM to adapt its functionality tothe required performance. In a practical application,those components that are not used can be turned off byusing a power-down control in order to save powerconsumption.In case resonation is enabled and considering a lin-ear model for the embedded quantizers, it can beshown that the NTF of the proposed architecture isgiven by:(1)where  stands for the inter-stage gain. Note that twoof the NTF zeroes are a function of , whose value canbe optimally chosen to maximize the Sig-nal-to-(Noise+Distortion) Ratio (SNDR).This effect is illustrated in Fig.2 for an OSR of 4and embedded quantizers with 4-bit resolution. Theoptimum values of  for an inter-stage gain of 1and 4 are roughly 0.4 and 0.1, which can be easilyimplemented using capacitor ratios of 2/5 and 1/10,respectively. If there is no signal scaling along the cas-cade ( ), the resolution is increased in 11dB,whereas if , an increment of 23dB is achieved.For the sake of completeness, Fig.3(a) shows theoptimal location of the NTF zeroes in the unity-circlefor oversampling ratios of 4, 8 and 16. The effect on thenoise shaping is depicted in Fig.3(b) by representingthe NTF for the different cases together with their cor-responding signal BandWidths (BWs).Note that an increase of  (to reduce the quantiza-tion noise) yields a reduction of the feedback coeffi-cient . In practice, this results in a smallercapacitor ratio, which makes the electrical implemen-tation more difficult and prone to circuit non-idealities.However, the value of  can be easily implementedif the oversampling ratio is low enough because —asillustrated in Fig.3(a)— a reduction of the OSR meansan increase of K. Therefore, the resonation provided bySr SLNTF z( ) 1 z1––( )– 2 1 2 K–( ) z 1–⋅ z 2–+–[ ]⋅d----------------------------------------------------------------------------------------=dK0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1–80–75–70–65–60–55–500 0.05 0.1 0.15 0.2 0.25–80–75–70–65–60–55–50 Fig. 2: Variation of the in-band quantization noise with  for: (a) , (b)  (  and ).K d⁄ d 1= d 4= OSR 4= B1 B2 4= =(b)(a)11dB23dBK d⁄ K d⁄K = 0.4K = 0.4In-band quantization noise (dB)In-band quantization noise (dB)K d⁄d 1=d 4=10-3 10-2 10-1 100–150–100–50050|NTF(f)|2  (dB)Normalized frequency–1 –0.5 0 0.5 1–1–0.8–0.6–0.4–0.200.20.40.60.8122Real partImaginary part Fig. 3: Optimum distribution of NTF zeroes in the proposed resonation-based ΣΔM for different oversampling ratios:(a) Location of zeroes in the unit circle, (b) NTF vs. frequency (d = 1).(a) (b)OSR3 = 4OSR2 = 8OSR1 = 16OSR1 = 16OSR2 = 8OSR3 = 4 K1 = 0.027K3 = 0.4042BW1 (OSR1 = 16)BW2 (OSR2 = 8)BW3 (OSR3 = 4)1 z 1––( )4K1 = 0.027K3 = 0.4042K3 = 0.4042K2 = 0.109K2 = 0.109K1 = 0.027K 2 = 0.109K = 0dK d⁄K d⁄the proposed architecture is specially suited for wide-band applications with low OSR.Fig.4 shows the conceptual SC implementation ofthe modulator in Fig.1, in which the required analogadditions are implemented by passive SC networks inorder to save power. The required analog coefficientsare implemented as capacitor ratios using capacitors to ,  and . Note that a number ofcapacitors in Fig.4 have negative values; in the actualfully differential implementation, the negative valuewould be implemented by swapping the correspondingcapacitors in the positive and negative signal branches.The use of passive SC analog additions involves areduction of the full scale at the quantizer input and,consequently, a compression of the references and thequantizers voltage levels to be used [12]. For instance,if the distribution of the charge in the capacitors of thefirst-stage analog adder during phase  is considered,the resulting scaling factor is(2)where Cquant stands for the input capacitance of thequantizer.In order to get a robust modulator implementationit is desirable to have the same scaling regardless of theuse of resonation. However, note from (2) that thedenominator term  equals zero in case res-onation is not employed, and thus the scaling factorvaries from the one obtained with resonation. Let usassumed that , , , a 4-bitquantizer and 10-fF input capacitance for the quantizercomparators; then the corresponding scaling factorwould be 0.234. If resonation is not employed Fig. 4: SC schematic of the proposed reconfigurable ΣΔM (single-ended version).K/d.Cin1K/d.Cin1+−φ1φ1φ2φ2Cs1Cs1OA1 +−φ1φ1φ2φ2Cs2Cs2OA2φ1φ2φ2φ1Cin1−+φ1φ2Cin12Cin1B1y1 +−yDIGITALCANCELATIONLOGICφ1φ2Cs1 B1Sr+−φ1φ1φ2φ2Cs3Cs3OA3 +−φ1φ1φ2φ2Cs4Cs4OA4φ1φ2φ2φ1Cin2−+φ1φ2dCin22Cin2B2φ1φ2dCs3y2φ1B2-KCin2DAC(1-z-1)2Sr Sr1/d-dCs3-2dCs3-dCs3-dCin2-2dCin2-dCin2-KCin2DACDAC (+DEM)SLSLSLSLSLφ2SrSr-KCs3SrSr-KCs3xCs1 Cs4 Cin1 Cin2φ1Cin14Cin1 2K d⁄ Cin1⋅ Cquant+ +----------------------------------------------------------------------2K d⁄ Cin1⋅Cin1 2pF= d 4= K 0.4=( ), the compression would be 0.245. In thisexample, a good choice for the reference compressionin both cases is 0.25, thus making easier the implemen-tation of the resulting voltage levels. Besides, thanks tothe location of the addition in the modulator chain, asmall variation of the scaling factor —as the one in thisexample— will have almost no impact on the modula-tor resolution. Note that the same applies to the sec-ond-stage analog addition.III. CASE STUDYIn order to show the reconfigurability of the pro-posed ΣΔM architecture, a case study is presented con-sidering the specifications and standards listed inTable I. Table II shows the values of the modulatordesign parameters that are reconfigured for the differ-ent operation modes, namely: NTF order ( ), reso-nation coefficient ( ) and OSR. Note that differentoversampling ratios —and their corresponding sam-pling frequencies (fs)— are employed in order to copewith the required resolution of each signal bandwidth.Note that in those operation modes in which no reso-nation is used (GSM, UMTS and Wi-Max), theswitches responsible for the last-stage error feedback(  in Fig.1) are disconnected. Additionally, in GSMmode only the first stage is working —with switches and  disconnected— whereas all the integratorsand comparators of the second stage are turned off.Global resonation is used only in WLAN mode. Inthis case, the rounded optimal feedback coefficient is, resulting in a shift of two zeroes of theNTF from 0 to . Note that thanks to this opti-mum distribution of the NTF zeroes —together withthe employment of an inter-stage scaling —, thein-band noise is minimized as shown in Fig.2(b).IV. SIMULATION RESULTSSeveral behavioral simulations have been per-formed using SIMSIDES, a Simulink-basedtime-domain simulator for ΣΔ modulators [13]. In alloperation modes, 4-bit internal quantizers and a 1-Vreference voltage were considered. Additionally, noise, sampled by 0.25-pF sampling capacitors,is introduced at the first integrator in all simulations.The embedded Digital-to-Analog Converters (DACs)are assumed linear, although dynamic element match-ing will be required in practice at least in the first stageof the cascade.Fig.5 shows the modulator output spectra for allthe operation modes. In GSM [Fig.5(a)], the in-banderror is dominated by thermal noise, whereas in UMTSK 0=TABLE I. SPECIFICATIONS FOR THE ΣΔM IN THE CASE STUDYStandard GSM UMTSaa. Although the bandwidth of UMTS is 3.84 MHz, it has been expandedto 4MHz in order to easily implement the sampling frequency.Wi-Max WLANSNDR (bit) 14 12 8 10BW (MHz) 0.2 4 20 20TABLE II. RESONATION COEFF, MODULATOR ORDER, OSR AND dStandard GSM UMTS Wi-Maxaa. Note that resonation could also be employed in this case if a largerresolution is demanded.WLANOrder (L) 2 4Inter-stage gain (d) ---- 4K 0 (No resonation) 0.4K/d 0 (No resonation) 0.1OSR 100 10 4fs (MHz) 40 80 160LK d⁄SrSr SLK d⁄ 0.1=0.8 j0.6±d 4=kT C⁄10-5 10-4 10-3 10-2 10-1 100–150–100–500PSD x freq. bin (dB)(c)BW = 20MHz10-5 10-4 10-3 10-2 10-1 100–150–100–500PSD x freq. bin (dB)10-5 10-4 10-3 10-2 10-1 100–150–100–500PSD x freq. bin (dB)10-5 10-4 10-3 10-2 10-1 100–150–100–500Normalized frequencyPSD x freq. bin (dB) Fig. 5: Modulator spectra of the different modes: (a) GSM,(b) UMTS, (c) Wi-Max, (d) WLAN (-6dBFS inputlevel, 64k-point FFTs).(a)(b)(d)BW = 200kHzBW = 4MHzBW = 20MHz[Fig.5(b)] the larger error term is not clearly definedbetween thermal or quantization noise. The effect ofresonation can be clearly distinguished by comparingFig.5(c) and (d), corresponding to Wi-Max andWLAN, respectively. Note that in WLAN, resonationreduces the in-band quantization error power as com-pared to Wi-Max. This is illustrated in Fig.6 where theSNDR is represented versus the input signal amplitude.Note that the effective resolution for WLAN is approx-imately 9dB larger than that for Wi-Max.The sensitivity to noise leakages due to capacitormismatch has been studied on the basis of Monte Carlosimulation. Fig.7 shows the SNDR at -6dBFS obtainedfor a 50-run Monte Carlo simulation considering astandard deviation of 0.1% in all capacitors. The mean[  (bits)] and the standard deviation ( ) of the result-ing effective modulator resolutions are also shown foreach operation mode. Note that the use of resonation inthe WLAN mode introduces no appreciable perfor-mance degradation when compared to the rest of oper-ation modes.Fig.8 shows the effect of the amplifiers finite DCgain on the modulator effective resolution for all theoperation modes. Note that the impact of the amplifiersgain on the modulator performance is considerablylower in GSM when compared to the rest of standards.This is due to the topology used for the ΣΔM in the for-mer case (single loop), which does not present the sen-sitivity to noise leakages inherent to cascadetopologies (used in the remaining standards). In thecase of UMTS and Wi-Max, there is no appreciabledegradation for amplifiers gains above 40dB. Thisvalue raises to 50dB for WLAN, which is still not ademanding requirement in practice.An appealing advantage that comes from the useof unity STFs is the subsequent reduction of the ampli-fiers output swing. This is illustrated in Fig.9 by plot-ting the histogram of the integrators outputs obtainedfrom the operation of the proposed modulator in alloperation modes. Note that the required output swingis only  for the 1st and 3rd operational ampli-fiers (OA1 and OA3), whereas it reduces to for the 2nd and 4th ones (OA2 and OA4). This trans-lates into an excellent linearity behavior for the pro-posed architecture.The latter is illustrated in Fig.10 by plotting theeffect of the amplifier gain non-linearity on the modu-lator SNDR. In this simulation, a finite gain of 55dB isconsidered for all amplifiers, while varying the2nd-order non-linearity of the DC gain for the amplifi-ers in the first stage of the cascade. Note that therobustness of the proposed ΣΔM to non-linearities isquite high, even if resonation is used to increase theeffective modulator resolution.μ σ–40 –35 –30 –25 –20 –15 –10 –5 0 530405060708090100Input level (dBFS)SNDR (dB)  UMTSGSM Fig. 6: Modulator SNDR versus input level(normalized to full scale).WLANWi–Max8 9 10 11 12 13 14 1500.51.01.52.02.53.03.54.04.55.0SNDR (bit)# of occurrences   Fig. 7: SNDR variation considering a 0.1% capacitor mismatch(-6dBFS input level, 50-run Monte Carlo simulation).Wi-MaxL = 4d = 4K = 0WLANL = 4d = 4K = 0.4UMTSL = 4d = 4K = 0GSML = 2μ 9.0=σ 3%=μ 10.6=σ 2%=μ 12.3=σ 2%=μ 14.4=σ 7%=10 15 20 25 30 35 40 45 50 55 60 65354045505560657075808590Amplifiers DC gain (dB)SNDR (dB)   Fig. 8: SNDR vs. finite DC gain of the amplifiers(-6dBFS input level).UMTSGSMWLANWi–Max0.15V±0.10V±–0.2 –0.15 –0.1 –0.05 0 0.05 0.1 0.150100200300400500600700800Output voltage (V)# of occurrences   OA1OA2OA3OA4OA1OA3 OA2OA4 Fig. 9: Histogram of the integrators outputs.V. CONCLUSIONSA new multi-functional cascade ΣΔM architecturehas been presented. This architecture is capable toreconfigure the order of the quantization noise filteringand to resonate through switchable feedbackinter-stage paths. Additionally, it achieves high linear-ity with reduced output swing requirements by usingunity STFs in both cascaded stages. These characteris-tics make the proposed modulator very appropriate forthe implementation of low-voltage multi-mode A/Dconversion, where the resolution of wideband stan-dards can be easily increased by means of adaptiveglobal resonation. A case study covering GSM,UMTS, Wi-Max and WLAN standards has been dis-cussed in order to show the capabilities of the proposedmodulator to perform the A/D conversion in future 4Gwireless multi-standard hand-held devices.VI. REFERENCES[1] X. Li and M. Ismail: Multi-standard CMOS wireless receiv-ers: analysis and design. Kluwer Academic Publishers,2002.[2] T. Burger et al.: “A 13.5mW 185-Msample/s ΔΣ Modulatorfor UMTS/GSM Dual-Standard IF Reception”. IEEE J. ofSolid-State Circuits, pp. 1868-1878, Dec. 2001.[3] T.M.R. Miller et al.: “A Multibit Sigma-Delta ADC forMultimode Receivers”. IEEE J. of Solid-State Circuits, pp.475-482, March 2003.[4] G. Gomez et al.: “A 1.5V 2.4/2.9mW 79/50dB DR ΣΔ Mod-ulator for GSM/WCDMA in 0.13μm Digital Process”.Proc. of ISSCC, pp. 242-490, 2002.[5] A. Dezzani et al.: “A 1.2-V Dual-Mode WCDMA/GPRSΣΔ Modulator”. Proc. of ISSCC, pp. 58-59, 2003.[6] J.H. Shim et al.: “A Third-Order ΣΔ Modulator in 0-18-μmCMOS With Calibrated Mixed-Mode Integrators”. IEEE J.of Solid-State Circuits, pp. 918-925, April 2005.[7] J. Lim et al.: “A Low-Power Sigma-Delta Modulator forWireless Communication Receivers using Adaptive Bias-ing Circuitry and Cascaded comparator scheme”. AnalogIntegrated Circuits and Signal Processing, pp. 359-365,Sept. 2006.[8] T. Christen et al.: “A 0.13μm CMOSEDGE/UMTS/WLAN Tri-Mode ΣΔ ADC with -92dBTHD”. Proc. of ISSCC, pp. 240-241, 2007.[9] A. Morgado et al.: “An Adaptive ΣΔ Modulator forMulti-Standard Hand-held Wireless Devices”. Proc. ofASSCC, pp. 232-235, November 2007.[10] J. Silva et al.: “Wideband low-distortion delta-sigma ADCtopology”. IEE Electronics Letters, vol. 37, pp. 737-738,June 2001.[11] M. Sanchez-Renedo et al.: “A 2-2 Discrete Time CascadedΣΔ Modulator With NTF Zero Using Interstage Feed-back”. Proc. of ICECS, pp. 954-957, 2006.[12] J. Silva, High-Performance Delta-Sigma Analog-to-DigitalConverters. Ph.D. Thesis, Oregon State University, 2004.[13] J. Ruíz-Amaya et al.: “High-level synthesis ofswitched-capacitor, Switched-Current and Continu-ous-Time ΣΔ Modulators Using SIMULINK-BasedTime-Domain Behavioral Models”. IEEE Trans. on Cir-cuits and Systems-I, vol. 52, pp. 1795-1810, Sept. 2005. 103 102 10145505560657075808590Amplifier gain non-linearity (%)SNDR (dB)   Fig. 10: SNDR vs. non-linearity of the amplifier gain(-6dBFS input level, 55-dB amplifier gain).UMTSGSMWLANWi–Max

A novel low-voltage reconfigurable ΣΔ modulator for 4G wireless receivers

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A novel low-voltage reconfigurable ΣΔ modulator for 4G wireless receivers

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idUS. Depósito de Investigación Universidad de Sevilla