Hybrid receiver study

The results are presented of a 4 month study to design a hybrid analog/digital receiver for outer planet mission probe communication links. The scope of this study includes functional design of the receiver; comparisons between analog and digital processing; hardware tradeoffs for key components including frequency generators, A/D converters, and digital processors; development and simulation of the processing algorithms for acquisition, tracking, and demodulation; and detailed design of the receiver in order to determine its size, weight, power, reliability, and radiation hardness. In addition, an evaluation was made of the receiver's capabilities to perform accurate measurement of signal strength and frequency for radio science missions

Control Theory in Engineering

The subject matter of this book ranges from new control design methods to control theory applications in electrical and mechanical engineering and computers. The book covers certain aspects of control theory, including new methodologies, techniques, and applications. It promotes control theory in practical applications of these engineering domains and shows the way to disseminate researchers’ contributions in the field. This project presents applications that improve the properties and performance of control systems in analysis and design using a higher technical level of scientific attainment. The authors have included worked examples and case studies resulting from their research in the field. Readers will benefit from new solutions and answers to questions related to the emerging realm of control theory in engineering applications and its implementation

Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation

Silicon compilation

Silicon compilation is a term used for many different purposes. In this paper we define silicon compilation as a mapping from some higher level description into layout. We define the basic issues in structural and behavioral silicon compilation and some possible solutions to those issues. Finally, we define the concept of an intelligent silicon compiler in which the compiler evaluates the quality of the generated design and attempts to improve it if it is not satisfactory

Fuzzy current analysis-based fault diagnostic of induction motor using hardware co-simulation with field programmable gate array

Introduction. Presently, signal analysis of stator current of induction motor has become a popular technique to assess the health state of asynchronous motor in order to avoid failures. The classical implementations of failure detection algorithms for rotating machines, based on microprogrammed sequential systems such as microprocessors and digital signal processing have shown their limitations in terms of speed and real time constraints, which requires the use of new technologies providing more efficient diagnostics such as application specific integrated circuit or field programmable gate array (FPGA). The purpose of this work is to study the contribution of the implementation of fuzzy logic on FPGA programmable logic circuits in the diagnosis of asynchronous machine failures for a phase unbalance and a missing phase faults cases. Methodology. In this work, we propose hardware architecture on FPGA of a failure detection algorithm for asynchronous machine based on fuzzy logic and motor current signal analysis by taking the RMS signal of stator current as a fault indicator signal. Results. The validation of the proposed architecture was carried out by a co-simulation hardware process between the ML402 boards equipped with a Virtex-4 FPGA circuit of the Xilinx type and Xilinx system generator under MATLAB/Simulink. Originality. The present work combined the performance of fuzzy logic techniques, the simplicity of stator current signal analysis algorithms and the execution power of ML402 FPGA board, for the fault diagnosis of induction machine achieving the best ratios speed/performance and simplicity/performance. Practical value. The emergence of this method has improved the performance of fault detection for asynchronous machine, especially in terms of hardware resource consumption, real-time online detection and speed of detection.Вступ. В даний час аналіз сигналу струму статора асинхронного двигуна став популярним методом оцінки стану працездатності асинхронного двигуна, щоб уникнути відмов. Класичні реалізації алгоритмів виявлення несправностей машин, що обертаються, засновані на мікропрограмних послідовних системах, таких як мікропроцесори і цифрова обробка сигналів, показали свої обмеження з точки зору швидкості та обмежень у реальному часі, що вимагає використання нових технологій, що забезпечують більш ефективну діагностику. наприклад, інтегральна схема для конкретної програми або програмована вентильна матриця (FPGA). Метою даної є дослідження внеску реалізації нечіткої логіки на програмованих логічних схемах FPGA в діагностику відмов асинхронних машин при несиметрії фаз і обривах фази. Методологія. У цій роботі ми пропонуємо апаратну архітектуру на FPGA алгоритму виявлення відмов асинхронної машини на основі нечіткої логіки та аналізу сигналів струму двигуна, приймаючи середньоквадратичний сигнал статора струму як сигнал індикатора несправності. Результати. Валідація запропонованої архітектури проводилася шляхом апаратного моделювання між платами ML402, оснащеними схемою Virtex-4 FPGA типу Xilinx та генератором системи Xilinx під керуванням MATLAB/Simulink. Оригінальність. Дана робота поєднала в собі ефективність методів нечіткої логіки, простоту алгоритмів аналізу сигналів струму статора та виконавчу потужність плати ML402 FPGA для діагностики несправностей асинхронних машин, досягаючи найкращих співвідношень швидкість/продуктивність та простота/продуктивність. Практична цінність. Поява цього методу покращила продуктивність виявлення несправностей асинхронної машини, особливо з точки зору споживання апаратних ресурсів, онлайн-виявлення в реальному часі та швидкості виявлення

Application of bit-slice microprocessors to digital correlation in spread spectrum communication systems

This thesis describes the application of commercially available microprocessors and other VLSI devices to high-speed real-time digital correlation in spread spectrum and related communication applications. Spread spectrum communications are a wide-band secure communication system that generate a very broad spectral bandwidth signal that is therefore hard to detect in noise. They are capable of rejecting intentional or unintentional jamming, and are insensitive to the multipath and fading that affects conventional high frequency systems. The bandwidth of spread spectrum systems must be large to obtain a significant performance improvement. This means that the sequence rate must be fast and therefore very fast microprocessors will be required when they are used to perform spread spectrum correlation. Since multiplication cannot be performed efficiently by microprocessors considerable work, since 1974, has been published in the literature which is devoted to minimising the requirement of multiplications in digital correlation and other signal processing algorithms. These fast techniques are investigated and implemented using general-purpose microprocessors. The restricted-bandwidth problem in microprocessor-based digital correlator has been discussed. A new implementation is suggested which uses bit-slice devices to maintain the flexibility of microprocessor-based digital correlation without sacrificing speed. This microprocessor-based system has been found to be efficient in implementing the correlation process at the baseband in the digital domain as well as the post-correlation signal processing- demodulation, detection and tracking, especiaJIy for low rate signals. A charge coupled-device is used to obtain spectral density function. An all-digital technique which is programmable for any binary waveform and can be used for achieving initial acquisition and maintaining synchronisation in spread spectrum communications is described. Many of the practical implementation problems are discussed. The receiver performance, which is measured in terms of the acquisition time and the bit-error rate, is also presented and results are obtained which are close to those predicted in the system simulations

The distributed computer system

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University

Fault-tolerant computer study

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed