Scale up of advanced packaging and system integration for hybrid technologies

This paper presents an overview of challenges in system integration for 2.5D/3D assemblies, including copackaged optics and electronics, MEMS and microfluidics. It addresses the gap between early-stage prototypes and volume manufacturing that need true advanced packaging and system integration to realize their complex multi-technology devices. This is done by means of a virtual demonstrator that include both 2.5D/3D assemblies of ASICs and integrated photonic devices, as well as MEMS and microfluidics devices. It also addresses lowering the cost barrier for users accessing these technologies for their products, such that it will enable an increased uptake of system integration by the industry at large

MICROELECTRONICS PACKAGING TECHNOLOGY ROADMAPS, ASSEMBLY RELIABILITY, AND PROGNOSTICS

This paper reviews the industry roadmaps on commercial-off-the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due tothe breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down-selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC). The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA). The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN), a data-driven PHM, was discussed in details. Finally, it presented inter- and extra-polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies

Book of Knowledge (BOK) for NASA Electronic Packaging Roadmap

The objective of this document is to update the NASA roadmap on packaging technologies (initially released in 2007) and to present the current trends toward further reducing size and increasing functionality. Due to the breadth of work being performed in the area of microelectronics packaging, this report presents only a number of key packaging technologies detailed in three industry roadmaps for conventional microelectronics and a more recently introduced roadmap for organic and printed electronics applications. The topics for each category were down-selected by reviewing the 2012 reports of the International Technology Roadmap for Semiconductor (ITRS), the 2013 roadmap reports of the International Electronics Manufacturing Initiative (iNEMI), the 2013 roadmap of association connecting electronics industry (IPC), the Organic Printed Electronics Association (OE-A). The report also summarizes the results of numerous articles and websites specifically discussing the trends in microelectronics packaging technologies

ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance

The semiconductor industry is entering a new age in which device scaling and cost reduction will no longer follow the decades-long pattern. Packing more transistors on a monolithic IC at each node becomes more difficult and expensive. Companies in the semiconductor industry are increasingly seeking technological solutions to close the gap and enhance cost-performance while providing more functionality through integration. Putting all of the operations on a single chip (known as a system on a chip, or SoC) presents several issues, including increased prices and greater design complexity. Heterogeneous integration (HI), which uses advanced packaging technology to merge components that might be designed and manufactured independently using the best process technology, is an attractive alternative. However, although the industry is motivated to move towards HI, many design and security challenges must be addressed. This paper presents a three-tier security approach for secure heterogeneous integration by investigating supply chain security risks, threats, and vulnerabilities at the chiplet, interposer, and system-in-package levels. Furthermore, various possible trust validation methods and attack mitigation were proposed for every level of heterogeneous integration. Finally, we shared our vision as a roadmap toward developing security solutions for a secure heterogeneous integration

Development of Silicon Photonic Multi Chip Module Transceivers

The exponential growth of data generation–driven in part by the proliferation of applications such as high definition streaming, artificial intelligence, and the internet of things–presents an impending bottleneck for electrical interconnects to fulfill data center bandwidth demands. Links now require bandwidths in excess of multiple Tbps while operating on the order of picojoules per bit, in addition to constraints on areal bandwidth densities and pin I/O bandwidth densities. Optical communications built on a silicon photonic platform offers a potential solution to develop power efficient, high bandwidth, low attenuation, small footprint links, all while building off the mature CMOS ecosystem. The development of silicon photonic foundries supporting multi project wafer runs with associated process design kit components supports a path towards widespread commercial production by increasing production volume while reducing fabrication and development costs. While silicon photonics can always be improved in terms of performance and yield, one of the central challenges is the integration of the silicon photonic integrated circuits with the driving electronic integrated circuits and data generating compute nodes such as CPUs, FPGAs, and ASICs. The co-packaging of the photonics with the electronics is crucial for adoption of silicon photonics in datacenters, as improper integration negates all the potential benefits of silicon photonics. The work in this dissertation is centered around the development of silicon photonic multi chip module transceivers to aid in the deployment of silicon photonics within data centers. Section one focuses on silicon photonic integration and highlights multiple integrated transceiver prototypes. The central prototype features a photonic integrated circuit with bus waveguides with WDM microdisk modulators for the transmitter and WDM demuxes with drop ports to photodiodes for the receiver. The 2.5D integrated prototype utilizes a thinned silicon interposer and TIA electronic integrated circuits. The architecture, integration, characterization, performance, and scalability of the prototype are discussed. The development of this first prototype identified key design considerations necessary for designing multi chip module silicon photonic prototypes, which will be addressed in this section. Finally, other multi chip module silicon photonic prototypes will be overviewed. These include a 2.5D integrated transceiver with a different electronic integrated circuit TIA, a 3D integrated receiver, an active interposer network on chip, and a 2.5D integrated transceiver with custom electronic integrated circuits. Section two focuses on research that supports the development of silicon photonic transceivers. The thermal crosstalk from neighboring microdisk modulators as a function of modulator pitch is investigated. As modulators are placed at denser pitches to accommodate areal bandwidth density requirements in transceivers, this thermal crosstalk will become significant. In this section, designs and results from several iterations of custom microring modulators are reported. Custom microring modulators allow for scaling up the number of channels in microring transceivers by offering the ability to fabricate variable resonances and provide a platform for further innovation in bandwidth, free spectral range, and energy efficiency. The designs and results of higher order modulation format modulators, both microring based and Mach Zehnder based, are discussed. High order modulators offer a path towards scaling transceiver total throughput without having to increase the channel counts or component bandwidth. Together, the work in these two sections supports the development of silicon photonic transceivers to aid in the adoption of silicon photonics into data generating systems

異種ダイレット積層を用いたフレキシブルハイブリッドデバイスの集積技術に関する研究

Tohoku University福島誉史課

Integrated silicon photonic packaging

Silicon photonics has garnered plenty of interests from both the academia and industry due to its high-speed transmission potential as well as sensing capability to complement silicon electronics. This has led to significant growth on the former, valuing at US$626.8M in 2017 and is expected to grow 3-fold to US$ 1,988.2M by 2023, based on data from MarketsandMarkets™. Silicon photonics’ huge potential has led to worldwide attention on fundamental research, photonic circuit designs and device fabrication technologies. However, as with silicon electronics in its early years, the silicon photonics industry today is extremely fragmented with various chip designs and layouts. Most silicon photonic devices fabricated are not able to reach the hand of consumers, due to a lack of information related to packaging design rules, components and processes. The importance of packaging technologies, which play a crucial role in turning photonic circuits and devices into the final product that end users can used in their daily lives, has been overlooked and understudied. This thesis aims to – 1. fill the missing gap by adapting existing electronics packaging techniques, 2. assess its scalability, 3. assess supply chain integration and finally 4. develop unique packaging approaches specifically for silicon photonics. The first section focused on high density packaging components and processes using University of California, Berkeley’s state-of-the-art silicon photonic MEMS optical switches as test devices. Three test vehicles were developed using (1) via-less ceramic and (2) spring-contacted electrical interposers for 2D integration and (3) through-glass-via electrical interposers for 2.5D heterogeneous integration. A high density (1) lidless fibre array and (2) a 2D optical interposer, which allows pitch-reduction of optical waveguides were also developed in this thesis. Together, these components demonstrated the world’s first silicon 2 photonic MEMS optical switch package and subsequently the highest density silicon photonic packaging components with 512 electrical I/Os and 272 optical I/Os. The second section then moved away from active optical coupling that was used in the former, investigating instead passive optical packaging concepts for the future. Two approaches were investigated - (1) grating-to-grating and (2) evanescent couplings. The former allows the development of pluggable packages, separating fibre coupling away from the device while the latter allows simultaneous optical and electrical packaging on a glass wafer in a single process. Lastly, the knowhow and concepts developed in this thesis were compiled into packaging design rules and subsequently introduced into H2020-MORPHIC, PIXAPP packaging training courses (as a trainer) and other packaging projects within the group

3D Hybrid Integration for Silicon Photonics

Silicon photonics (SiPh) has emerged as a photonic integrated circuit (PIC) platform, especially for high volume applications. Integrated laser sources, however, remain a challenge. SiPh foundries have existed for more than 10 years but still don’t offer a qualified process with integrated lasers. Direct heteroepitaxy of group III-V materials on silicon is still immature and suffers from reliability issues. Heterogeneous and hybrid integration techniques, however, have been pursued in research and by industry and present a practical near-term solution for laser integration. Heterogenous approaches based on wafer bonding involve the bonding of bare III-V epitaxial material to silicon on insulator (SOI), co-fabrication, and evanescent light coupling. The laser active medium is thermally isolated from the silicon substrate by the buried oxide layer limiting the laser efficiency at high temperature. Hybrid integration approaches, such as the butt coupling of fabricated III-V lasers to SOI waveguides, may address the thermal issue. However, the main limitation for butt coupling is the significant mode mismatch of the waveguides that imposes a strict alignment requirement.In this thesis the novel 3D hybrid integration technique for SiPh, addressing the aspects of thermal performance and alignment tolerance, was proposed and demonstrated for the first time. This approach is based on the flip-chip integration of indium phosphide (InP) reflective semiconductor optical amplifiers (RSOAs) containing total internal reflection turning mirrors for surface emission. Light is coupled to the SOI waveguides through surface grating couplers. This technique yields increased alignment tolerance compared to butt coupling. Flip-chip integration also allows the RSOA chip to be bonded P-side down directly to the silicon substrate. In this way, the heat generated in the active region can dissipate more efficiently in the silicon. 3D hybrid integration can be carried out at wafer level in a backend step for high throughput manufacturing, and also allow for the integration of InP PICs on silicon interposers for large-scale electronic-photonic integration.A tunable laser was demonstrated with 3D hybrid integration demonstrating a side-mode suppression ratio up to 43 dB. Greater than 4 mW of optical power was coupled into SiPh waveguide and more than 20 nm wavelength tuning range was achieved. A linewidth of 1.5 MHz and relative intensity noise of -132 dB/Hz were demonstrated. A low thermal impedance of 6.2 ℃/W was extracted experimentally from a 3D hybrid laser that was bonded to the silicon substrate, demonstrating a factor of three improvement over a laser that was bonded above the SOI layer. To improve coupling efficiency, various advanced silicon surface grating couplers as well as dilute waveguide RSOAs were investigated. Coupling efficiency up to 85\% can be achieved while also maintaining an alignment tolerant implementation

Transfer printing based microassembly and colloidal quantum dot film integration

Micro / nanoscale manufacturing requires unique approaches to accommodate the immensely different characteristics of the miniscule objects due to their high surface area to volume ratio when compared with macroscale objects. Therefore, surface forces are much more dominating than body forces, which causes the significant difficulty of miniscule object manipulation. Because of this challenge, monolithic microfabrication relying on photolithography has been the primary method to manufacture micro / nanoscale structures and devices in place of microassembly. However, by virtue of the two-dimensional (2D) nature of photolithography, formation of complex 3D shape architectures via monolithic microfabrication is inherently limited, which would otherwise enable improvements in performance and novel functionalities of devices. Furthermore, monolithic microfabrication is compatible only with materials which survive in a wet condition during photolithography. Delicate nanomaterials such as colloidal quantum dots cannot be processed via monolithic microfabrication. In this context, transfer printing has emerged as a method to transfer heterogeneous material pieces from their mother substrates to a foreign substrate utilizing a polymeric stamp in a dry condition. In this thesis, advanced modes of transfer printing are studied and optimized to enable a 3D microassembly called ‘micro-Lego’ and a novel strategy of quantum dot film integration. Micro-Lego involves transfer printing for material piece pick-and-place and thermal joining for irreversible permanent bonding of placed material pieces. A microtip elastomeric stamp is designed to advance transfer printing and thermal joining processes are optimized to ensure subsequent material bonding. The mechanical joining strength between material pieces assembled by micro-Lego are characterized by means of blister tests and the nanoindentation. Moreover, the electrical contact between two conducting materials formed by micro-Lego are examined. Lastly, inspired from the subtractive transfer printing technique, protocols of quantum dot film patterning using polymeric stamps made of a shape memory polymer as well as a photoresist are established for the convenient integration of quantum dots in various geometries and configurations as desired. Transfer printing-based micro / nanoscale manufacturing presented in this thesis opens up new pathways to manufacture not only complex 3D functional micro devices but also high resolution nano devices for unparalleled performance or for an unusual functionality, which are unattainable through monolithic microfabrication