Low power CMOS analog multipliers.

CMOS analog multiplier is a very important building block and programming element in analog signal processing. Although high-performance multipliers using bipolar transistors have been available for 40 years, CMOS multiplier implementation is still a challenging subject especially for low-power and low-noise circuit design. Since the supply voltage is normally fixed for analog multiplier structures, we use the total current to represent the power dissipation. Our basic idea for low power design of analog multipliers is to fit most of the transistors into the linear region, while at the same time keeping the drain-to-source voltage as low as possible to decease the drain current. And also, we use PMOS transistors for the devices working in the saturation region to further decrease the drain current and improve the linearity performance. Two low power CMOS analog multiplier designs have been proposed in this thesis. We gave detailed performance analysis and some design considerations for these structures. Cadence Hspice simulation verified our analysis. To ensure a fair comparison, we also simulated the performance of a previous multiplier structure, which was considered to be one of the best multiplier structures with low power and low noise performance. Extensive experiments and comparison for these structures show that the proposed CMOS analog multipliers have much less power dissipation than that of previous structures, while at the same time, satisfying other performance requirements. The proposed analog multipliers would be good choices in the applications where low power dissipation is an important consideration.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .L5. Source: Masters Abstracts International, Volume: 43-01, page: 0280. Adviser: Chunhong Chen. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004

Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007

High-Linearity Self-Biased CMOS Current Buffer

A highly linear fully self-biased class AB current buffer designed in a standard 0.18 mu m CMOS process with 1.8 V power supply is presented in this paper. It is a simple structure that, with a static power consumption of 48 mu W, features an input resistance as low as 89 Omega, high accuracy in the input-output current ratio and total harmonic distortion (THD) figures lower than -60 dB at 30 mu A amplitude signal and 1 kHz frequency. Robustness was proved through Monte Carlo and corner simulations, and finally validated through experimental measurements, showing that the proposed configuration is a suitable choice for high performance low voltage low power applications

A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation

The examined class of circuits includes voltage multipliers, current multipliers, linear V-I convertors, linear I-V convertors, current squaring circuits, and current divider circuits. Typical for these circuits is an independent control of the sum as well as the difference between two gate-source voltages. As direct use is made of the basic device characteristics, only a small number of transistors is required in the presented circuits

Low-voltage, low-power circuits for data communication systems

There are growing industrial demands for low-voltage supply and low-power consumption circuits and systems. This is especially true for very high integration level and very large scale integrated (VLSI) mixed-signal chips and system-on-a-chip. It is mainly due to the limited power dissipation within a small area and the costs related to the packaging and thermal management. In this research work, two low-voltage, low-power integrated circuits used for data communication systems are introduced. The first one is a high performance continuous-time linear phase filter with automatic frequency tuning. The filter can be used in hard disk driver systems and wired communication systems such as 1000Base-T transceivers. A pseudo-differential operational transconductance amplifier (OTA) based on transistors operating in triode region is used to achieve a large linear signal swing with low-voltage supplies. A common-mode (CM) control circuit that combines common-mode feedback (CMFB), common-mode feedforward (CMFF), and adaptive-bias has been proposed. With a 2.3V single supply, the filters total harmonic distortion is less than 44dB for a 2VPP differential input, which is due to the well controlled CM behavior. The ratio of the root mean square value of the ac signal to the power supply voltage is around 31%, which is much better than previous realizations. The second integrated circuit includes two LVDS drivers used for high-speed point-to-point links. By removing the stacked switches used in the conventional structures, both LVDS drivers can operate with ultra low-voltage supplies. Although the Double Current Sources (DCS) LVDS driver draws twice minimum static current as required by the signal swing, it is quite simple and achieves very high speed operation. The Switchable Current Sources (SCS) LVDS driver, by dynamically switching the current sources, draws minimum static current and reduces the power consumption by 60% compared to the previously reported LVDS drivers. Both LVDS drivers are compliant to the standards and operate at data rates up to gigabits-per-second

Analysis and design of high-transconductance RF mosfet voltage to-current converters

The research described in this thesis is concerned with analysis and design of "HighTransconductance RF MOSFET Voltage-to-Current (V-I) Converters". Various V-I converter circuits published in the past have been reviewed by the author in order to understand the different techniques employed to improve transconductance (Gt), linear operating range and total harmonic distortion (THO). Throughout this research, the emphasis has been to improve the above mentioned parameters. All the V-I converter circuits reported have been simulated using PSPICE and the results compared with the values obtained by theoretical analysis. Some of the results of this work have been already reported by the author in the technical literature. (See Chapter 9, at the end of this thesis, where reference to two publications by the author is given.) It was essential to obtain accurate CMOS device parameters values, such as Early Voltage, transconductance parameter ratios!! (gm/gds), X (gmbl'gm) and inter-electrode capacitances, to facilitate the design the prQcess. This was achieved using an extensive set of simulations for the transistor operating under different bias conditions. Furthermore, a measurement technique, thought to be novel, for the direct determination of the transconductance ratios!! and X is proposed. In the next part of the work several types of current mirror are compared against the standard current mirrors, using analytical and simulation methods. Furthermore several MOSFET V-I converter designs were critically reviewed to understand the various existing techniques and their limitations. Two novel techniques, Drain-Source Feedback Circuits (DSFCs) and Drain-Gate Feedback Circuits (OGFCs) ere implemented with a new temperature-compensation scheme, designed to operate well in an industrial environment (-40°C - +8S°C). It is found that the best types of V -I converters were the DSFCs which, offer a more accurate value of Gt (3.386mS) and the THO less than -S7dB for a differential input operating range SOOm V at 1 GHz with a 3V total rail voltage. The OGFC circuits were also meet the initial design targets, the value of THO is less then -SOdB, and operating in the Giga hertz frequency range is possible. Preliminary investigation on future work shows promising results

Realization of Integrable Low- Voltage Companding Filters for Portable System Applications

Undoubtedly, today’s integrated electronic systems owe their remarkable performance primarily to the rapid advancements of digital technology since 1970s. The various important advantages of digital circuits are: its abstraction from the physical details of the actual circuit implementation, its comparative insensitiveness to variations in the manufacturing process, and the operating conditions besides allowing functional complexity that would not be possible using analog technology. As a result, digital circuits usually offer a more robust behaviour than their analog counterparts, though often with area, power and speed drawbacks. Due to these and other benefits, analog functionality has increasingly been replaced by digital implementations. In spite of the advantages discussed above, analog components are far from obsolete and continue to be key components of modern electronic systems. There is a definite trend toward persistent and ubiquitous use of analog electronic circuits in day-to-day life. Portable electronic gadgets, wireless communications and the widespread application of RF tags are just a few examples of contemporary developments. While all of these electronic systems are based on digital circuitry, they heavily rely on analog components as interfaces to the real world. In fact, many modern designs combine powerful digital systems and complementary analog components on a single chip for cost and reliability reasons. Unfortunately, the design of such systems-on-chip (SOC) suffers from the vastly different design styles of analog and digital components. While mature synthesis tools are readily available for digital designs, there is hardly any such support for analog designers apart from wellestablished PSPICE-like circuit simulators. Consequently, though the analog part usually occupies only a small fraction of the entire die area of an SOC, but its design often constitutes a major bottleneck within the entire development process. Integrated continuous-time active filters are the class of continuous-time or analog circuits which are used in various applications like channel selection in radios, anti-aliasing before sampling, and hearing aids etc. One of the figures of merit of a filter is the dynamic range; this is the ratio of the largest to the smallest signal that can be applied at the input of the filter while maintaining certain specified performance. The dynamic range required in the filter varies with the application and is decided by the variation in strength of the desired signal as well as that of unwanted signals that are to be rejected by the filter. It is well known that the power dissipation and the capacitor area of an integrated active filter increases in proportion to its dynamic range. This situation is incompatible with the needs of integrated systems, especially battery operated ones. In addition to this fundamental dependence of power dissipation on dynamic range, the design of integrated active filters is further complicated by the reduction of supply voltage of integrated circuits imposed by the scaling down of technologies to attain twin objective of higher speed and lower power consumption in digital circuits. The reduction in power consumption with decreasing supply voltage does not apply to analog circuits. In fact, considerable innovation is required with a reduced supply voltage even to avoid increasing power consumption for a given signal to noise ratio (S/N). These aspects pose a great hurdle to the active filter designer. A technique which has attracted the attention of circuit designers as a possible route to filters with higher dynamic range per unit power consumption is “companding”. Companding (compression-expansion) filters are a very promising subclass of continuous-time analog filters, where the input (linear) signal is initially compressed before it will be handled by the core (non-linear) system. In order to preserve the linear operation of the whole system, the non-linear signal produced by the core system is converted back to a linear output signal by employing an appropriate output stage. The required compression and expansion operations are performed by employing bipolar transistors in active region or MOS transistors in weak inversion; the systems thus derived are known as logarithmic-domain (logdomain) systems. In case MOS transistors operated in saturation region are employed, the derived structures are known as Square-root domain systems. Finally, the third class of companding filters can also be obtained by employing bipolar transistors in active region or MOS transistors in weak inversion; the derived systems are known as Sinh-domain systems. During the last several years, a significant research effort has been already carried out in the area of companding circuits. This is due to the fact that their main advantages are the capability for operation in low-voltage environment and large dynamic range originated from their companding nature, electronic tunability of the frequency characteristics, absence of resistors and the potential for operations in varied frequency regions.Thus, it is obvious that companding filters can be employed for implementing high-performance analog signal processing in diverse frequency ranges. For example, companding filters could be used for realizing subsystems in: xDSL modems, disk drive read channels, biomedical electronics, Bluetooth/ZigBee applications, phaselocked loops, FM stereo demodulator, touch-tone telephone tone decoder and crossover network used in a three-way high-fidelity loudspeaker etc. A number of design methods for companding filters and their building blocks have been introduced in the literature. Most of the proposed filter structures operate either above 1.5V or under symmetrical (1.5V) power supplies. According to data that provides information about the near future of semiconductor technology, International Technology Roadmap for Semiconductors (ITRS), in 2013, the supply voltage of digital circuits in 32 nm technology will be 0.5 V. Therefore, the trend for the implementation of analog integrated circuits is the usage of low-voltage building blocks that use a single 0.5-1.5V power supply. Therefore, the present investigation was primarily concerned with the study and design of low voltage and low power Companding filters. The work includes the study about: the building blocks required in implementing low voltage and low power Companding filters; the techniques used to realize low voltage and low power Companding filters and their various areas of application. Various novel low voltage and low power Companding filter designs have been developed and studied for their characteristics to be applied in a particular portable area of application. The developed designs include the N-th order universal Companding filter designs, which have been reported first time in the open literature. Further, an endeavor has been made to design Companding filters with orthogonal tuning of performance parameters so that the designs can be simultaneously used for various features. The salient features of each of the developed circuit are described. Electronic tunability is one of the major features of all of the designs. Use of grounded capacitors and resistorless designs in all the cases makes the designs suitable for IC technology. All the designs operate in a low-voltage and low-power environment essential for portable system applications. Unless specified otherwise, all the investigations on these designs are based on the PSPICE simulations using model parameters of the NR100N bipolar transistors and BSIM 0.35μm/TSMC 0.25μm /TSMC 0.18μm CMOS process MOS transistors. The performance of each circuit has been validated by comparing the characteristics obtained using simulation with the results present in the open literature. The proposed designs could not be realized in silicon due to non-availability of foundry facility at the place of study. An effort has already been started to realize some of the designs in silicon and check their applicability in practical circuits. At the basic level, one of the proposed Companding filter designs was implemented using the commercially available transistor array ICs (LM3046N) and was found to verify the theoretical predictions obtained from the simulation results

Techniques of Energy-Efficient VLSI Chip Design for High-Performance Computing

How to implement quality computing with the limited power budget is the key factor to move very large scale integration (VLSI) chip design forward. This work introduces various techniques of low power VLSI design used for state of art computing. From the viewpoint of power supply, conventional in-chip voltage regulators based on analog blocks bring the large overhead of both power and area to computational chips. Motivated by this, a digital based switchable pin method to dynamically regulate power at low circuit cost has been proposed to make computing to be executed with a stable voltage supply. For one of the widely used and time consuming arithmetic units, multiplier, its operation in logarithmic domain shows an advantageous performance compared to that in binary domain considering computation latency, power and area. However, the introduced conversion error reduces the reliability of the following computation (e.g. multiplication and division.). In this work, a fast calibration method suppressing the conversion error and its VLSI implementation are proposed. The proposed logarithmic converter can be supplied by dc power to achieve fast conversion and clocked power to reduce the power dissipated during conversion. Going out of traditional computation methods and widely used static logic, neuron-like cell is also studied in this work. Using multiple input floating gate (MIFG) metal-oxide semiconductor field-effect transistor (MOSFET) based logic, a 32-bit, 16-operation arithmetic logic unit (ALU) with zipped decoding and a feedback loop is designed. The proposed ALU can reduce the switching power and has a strong driven-in capability due to coupling capacitors compared to static logic based ALU. Besides, recent neural computations bring serious challenges to digital VLSI implementation due to overload matrix multiplications and non-linear functions. An analog VLSI design which is compatible to external digital environment is proposed for the network of long short-term memory (LSTM). The entire analog based network computes much faster and has higher energy efficiency than the digital one

New Possibilities In Low-voltage Analog Circuit Design Using Dtmos Transistors

(Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2013(PhD) -- İstanbul Technical University, Institute of Science and Technology, 2013Bu çalışmada DTMOS yaklaşımı çok düşük besleme gerilimlerinde çalışan çok düşük güç tüketimli devrelere başarıyla uygulanmıştır. Tasarlanan devreler arasında OTA, OP-AMP, CCII gibi analog aktif yapı blokları, çarpma devresi, sadece-MOS yapılar gibi devreler bulunmaktadır. Tasarlanan devreler SPICE benzetimleri ile doğrulanmıştır. İleri yönde gövde kutuplamaya bağlı olarak DTMOS transistorun yapısından kaynaklanan, efektif olarak düşük eşik gerilimli çalışma özelliği nedeniyle, çok düşük güç tüketimli ve çok düşük gerilimli devrelerde DTMOS yaklaşımının geçerli bir alternatif olduğu bu çalışmayla gösterilmiştir. DTMOS yaklaşımının geniş bir alanda çeşitlilik gösteren analog devre yapılarında çok düşük besleme gerilimlerinde bile kabul edilebilir bir performansla kullanılabileceği bulunmuştur.In this study, DTMOS approach to the design of ultra low-voltage and ultra low-power analog circuits, has been successfully applied to the circuits ranging from EEG filtering circuits, speech processing filters in hearing aids, multipliers, analog active building blocks: OTA, OP-AMP, CCII to MOS-only circuits. The proposed circuits are verified with SPICE simulations. It is found that in designing ultra low-voltage, ultra low-power analog circuits, DTMOS approach is a viable alternative due to its inherent characteristic of effective low threshold voltage behaviour under forward body bias. This approach can be applied to several analog application subjects with acceptable performance under even ultra low supply voltages.DoktoraPh