Skybridge: A New Nanoscale 3-D Computing Framework for Future Integrated Circuits

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, continuing the traditional way of scaling to sub-20nm technologies is proving to be very difficult as MOSFETs are reaching their fundamental performance limits [1] and interconnection bottleneck is dominating IC operational power and performance [2]. Migrating to 3-D, as a way to advance scaling, has been elusive due to inherent customization and manufacturing requirements in CMOS architecture that are incompatible with 3-D organization. Partial attempts with die-die [3] and layer-layer [4] stacking have their own limitations [5]. We propose a new 3-D IC fabric technology, Skybridge [6], which offers paradigm shift in technology scaling as well as design. We co-architect Skybridge’s core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D template. Our extensive bottom-up simulations, accounting for detailed material system structures, manufacturing process, device, and circuit parasitics, carried through for several designs including a designed microprocessor, reveal a 30-60x density, 3.5x performance/watt benefits, and 10x reduction in interconnect lengths vs. scaled 16-nm CMOS [6]. Fabric-level heat extraction features are found to be effective in managing IC thermal profiles in 3-D. This 3-D integrated fabric proposal overcomes the current impasse of CMOS in a manner that can be immediately adopted, and offers unique solution to continue technology scaling in the 21st century

Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, scaling to sub-20nm technologies is proving to be challenging as MOSFETs are reaching their fundamental limits and interconnection bottleneck is dominating IC operational power and performance. Migrating to 3-D, as a way to advance scaling, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization. Partial attempts with die-die and layer-layer stacking have their own limitations. We propose a 3-D IC fabric technology, Skybridge[TM], which offers paradigm shift in technology scaling as well as design. We co-architect Skybridge's core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D template. Our extensive bottom-up simulations, accounting for detailed material system structures, manufacturing process, device, and circuit parasitics, carried through for several designs including a designed microprocessor, reveal a 30-60x density, 3.5x performance per watt benefits, and 10X reduction in interconnect lengths vs. scaled 16-nm CMOS. Fabric-level heat extraction features are shown to successfully manage IC thermal profiles in 3-D. Skybridge can provide continuous scaling of integrated circuits beyond CMOS in the 21st century.Comment: 53 Page

Cellular automata : a bridge between building variability and urban form control

In Porto Alegre, a Brazilian town with 1,5 million inhabitants, zoning guidelines assign similar density parameters but fail to be context-specific. As these regulations are linked to individual plot dimensions, physical growth resulted in heterogeneous and unpredictable urban space. The Floor Space Index (FSI) has been used as physical currency which influences the plot value there hence creating a straightjacket to architects wanting to explore new shapes. This research describes a simultaneous top-down and bottom-up strategy to allow urban rules to emulate architectural flexibility and, at the same time, to empower the city with morphological controls over the urban space. A proposed integrated model was set to generate a wide variety of geometries through the association of morpho-types urban blocks (topdown) to bottom-up strategies using cellular automata integrated to Rhinoceros’ Grasshopper as a generative tool. The model includes context sensibility and daylight evaluation but runs with a similar FSI to the existing urban regulations. The proposed model was applied to an existing block in Porto Alegre demonstrating to be an effective tool to support the design of urban rules. It also indicated possible paths for built environment model integration and the creation of innovative perfomative urban indexes as building’s porosity.O Plano Diretor da cidade de Porto Alegre paradoxalmente atribui índices de densidade por região geográfica ao passo que falha ao desconsiderar o contexto imediato. Uma vez que os índices aplicados estão associados às dimensões de cada lote, o crescimento do ambiente construído é restringido pela unidade de divisão territorial (lote) e resulta em um espaço urbano imprevisível e heterogêneo. Nesse contexto, o indicador de intensidade ‘Índice de Aproveitamento’ (IA) é usado como ‘moeda física’ pelos incorporadores, influenciando o valor do lote e limitando a exploração formal dos arquitetos, via de regra, a prismas regulares. Esta pesquisa propõe um modelo alternativo que une estratégias centralizadoras (top-down) e emergentes (bottom-up) a fim de possibilitar a flexibilidade arquitetônica e o controle da forma do espaço urbano simultaneamente. O modelo generativo proposto objetiva gerar geometrias variadas por meio da associação de tipologias morfológicas de quadra (controle) e autômatos celulares (emergente). O modelo gera edificações de IA similar ao existente e aos especificados no plano diretor ao mesmo tempo que é sensível ao contexto e avalia o desempenho de iluminação natural no ambiente de modelagem Rhinoceros 3D e programação visual Grasshopper. O modelo foi aplicado a uma quadra existente em Porto Alegre e os resultados demonstraram a sua eficácia como ferramenta de projeto para a concepção de regras urbanas. Os resultados indicaram a possibilidade de integração com modelos de outras naturezas e da criação de novos índices urbanos performativos como ‘porosidade’

Nasics: A `Fabric-Centric\u27 Approach Towards Integrated Nanosystems

This dissertation addresses the fundamental problem of how to build computing systems for the nanoscale. With CMOS reaching fundamental limits, emerging nanomaterials such as semiconductor nanowires, carbon nanotubes, graphene etc. have been proposed as promising alternatives. However, nanoelectronics research has largely focused on a `device-first\u27 mindset without adequately addressing system-level capabilities, challenges for integration and scalable assembly. In this dissertation, we propose to develop an integrated nano-fabric, (broadly defined as nanostructures/devices in conjunction with paradigms for assembly, inter-connection and circuit styles), as opposed to approaches that focus on MOSFET replacement devices as the ultimate goal. In the `fabric-centric\u27 mindset, design choices at individual levels are made compatible with the fabric as a whole and minimize challenges for nanomanufacturing while achieving system-level benefits vs. scaled CMOS. We present semiconductor nanowire based nano-fabrics incorporating these fabric-centric principles called NASICs and N3ASICs and discuss how we have taken them from initial design to experimental prototype. Manufacturing challenges are mitigated through careful design choices at multiple levels of abstraction. Regular fabrics with limited customization mitigate overlay alignment requirements. Cross-nanowire FET devices and interconnect are assembled together as part of the uniform regular fabric without the need for arbitrary fine-grain interconnection at the nanoscale, routing or device sizing. Unconventional circuit styles are devised that are compatible with regular fabric layouts and eliminate the requirement for using complementary devices. Core fabric concepts are introduced and validated. Detailed analyses on device-circuit co-design and optimization, cascading, noise and parameter variation are presented. Benchmarking of nanowire processor designs vs. equivalent scaled 16nm CMOS shows up to 22X area, 30X power benefits at comparable performance, and with overlay precision that is achievable with present-day technology. Building on the extensive manufacturing-friendly fabric framework, we present recent experimental efforts and key milestones that have been attained towards realizing a proof-of-concept prototype at dimensions of 30nm and below

New Design Techniques for Dynamic Reconfigurable Architectures

L'abstract è presente nell'allegato / the abstract is in the attachmen

A Modular Approach to Adaptive Reactive Streaming Systems

The latest generations of FPGA devices offer large resource counts that provide the headroom to implement large-scale and complex systems. However, there are increasing challenges for the designer, not just because of pure size and complexity, but also in harnessing effectively the flexibility and programmability of the FPGA. A central issue is the need to integrate modules from diverse sources to promote modular design and reuse. Further, the capability to perform dynamic partial reconfiguration (DPR) of FPGA devices means that implemented systems can be made reconfigurable, allowing components to be changed during operation. However, use of DPR typically requires low-level planning of the system implementation, adding to the design challenge. This dissertation presents ReShape: a high-level approach for designing systems by interconnecting modules, which gives a ‘plug and play’ look and feel to the designer, is supported by tools that carry out implementation and verification functions, and is carried through to support system reconfiguration during operation. The emphasis is on the inter-module connections and abstracting the communication patterns that are typical between modules – for example, the streaming of data that is common in many FPGA-based systems, or the reading and writing of data to and from memory modules. ShapeUp is also presented as the static precursor to ReShape. In both, the details of wiring and signaling are hidden from view, via metadata associated with individual modules. ReShape allows system reconfiguration at the module level, by supporting type checking of replacement modules and by managing the overall system implementation, via metadata associated with its FPGA floorplan. The methodology and tools have been implemented in a prototype for a broad domain-specific setting – networking systems – and have been validated on real telecommunications design projects

An Overlay Architecture for Pattern Matching

Deterministic and Non-deterministic Finite Automata (DFA and NFA) comprise the fundamental unit of work for many emerging big data applications, motivating recent efforts to develop Domain-Specific Architectures (DSAs) to exploit fine-grain parallelism available in automata workloads. This dissertation presents NAPOLY (Non-Deterministic Automata Processor Over- LaY), an overlay architecture and associated software that attempt to maximally exploit on-chip memory parallelism for NFA evaluation. In order to avoid an upper bound in NFA size that commonly affects prior efforts, NAPOLY is optimized for runtime reconfiguration, allowing for full reconfiguration in 10s of microseconds. NAPOLY is also parameterizable, allowing for offline generation of repertoire of overlay configurations with various trade-offs between state capacity and transition capacity. In this dissertation, we evaluate NAPOLY on automata applications packaged in ANMLZoo benchmarks using our proposed state mapping heuristic and off-shelf SAT solver. We compare NAPOLY’s performance against existing CPU and GPU implementations. The results show NAPOLY performs best for larger benchmarks with more active states and high report frequency. NAPOLY outperforms in 10 out of 12 benchmark suite to the best of state-of-the-art CPU and GPU implementations. To the best of our knowledge, this is the first example of a runtime-reprogrammable FPGA-based automata processor overlay

Sustainable Fashion and Textile Recycling

The clothing and textile industry is a resource-intensive industry and accounts for 3 to 10 percent of global carbon dioxide emissions. In addition, the industry is extremely linear and generates large amounts of waste. For the industry to move from a linear to a circular economy, several solutions are required along the value chain: upstream by working with resource efficiency, the longevity of textile products, and preventing waste; and downstream with techniques for sorting and recycling. In addition, solutions for traceability and transparency need to be developed and coordinated as accepted methods for sustainability measurements. This Special Issue (SI) "Sustainable Fashion and Textile Recycling" brings together areas of knowledge along the textile value chain to highlight the difficulties and opportunities that exist from both a broader perspective and in specific issues. In this SI, these 11 papers are mainly devoted to new research in traceability, design, textile production, and recycling. Each valuable article included in this Special Issue contributes fundamental knowledge for a transformation of the textile and fashion industry to take place. Numerous studies, solutions, and ideas need to be carried out to create the innovations that will become the reality of our future. Likewise, we need to learn from each other and take advantage of all the fantastic knowledge that is generated globally every day towards a better future for generations to come

A Dynamically Reconfigurable Parallel Processing Framework with Application to High-Performance Video Processing

Digital video processing demands have and will continue to grow at unprecedented rates. Growth comes from ever increasing volume of data, demand for higher resolution, higher frame rates, and the need for high capacity communications. Moreover, economic realities force continued reductions in size, weight and power requirements. The ever-changing needs and complexities associated with effective video processing systems leads to the consideration of dynamically reconfigurable systems. The goal of this dissertation research was to develop and demonstrate the viability of integrated parallel processing system that effectively and efficiently apply pre-optimized hardware cores for processing video streamed data. Digital video is decomposed into packets which are then distributed over a group of parallel video processing cores. Real time processing requires an effective task scheduler that distributes video packets efficiently to any of the reconfigurable distributed processing nodes across the framework, with the nodes running on FPGA reconfigurable logic in an inherently Virtual\u27 mode. The developed framework, coupled with the use of hardware techniques for dynamic processing optimization achieves an optimal cost/power/performance realization for video processing applications. The system is evaluated by testing processor utilization relative to I/O bandwidth and algorithm latency using a separable 2-D FIR filtering system, and a dynamic pixel processor. For these applications, the system can achieve performance of hundreds of 640x480 video frames per second across an eight lane Gen I PCIe bus. Overall, optimal performance is achieved in the sense that video data is processed at the maximum possible rate that can be streamed through the processing cores. This performance, coupled with inherent ability to dynamically add new algorithms to the described dynamically reconfigurable distributed processing framework, creates new opportunities for realizable and economic hardware virtualization.\u2