Channel routing optimization using a genetic algorithm

A modified approach for the application of Genetic Algorithm (GA) to the Channel Routing Problem has been proposed. The code based on the algorithm proposed in [1] has been implemented for the GA procedures of Initial Population Generation, Crossover, Mutation and Selection. A few improvements over the existing work have been made and the results so far obtained have been encouraging. Further experimentation is being done on the algorithm and other ideas generated during the development of the code are being implemented for faster convergence of the algorithm and for generation of more efficient results. Also application of variations of the GA technique like Vector GA and even other computationally intelligent techniques like Particle Swarm Optimization to the channel routing problem is being thought of

Distributed evolutionary algorithms and their models: A survey of the state-of-the-art

The increasing complexity of real-world optimization problems raises new challenges to evolutionary computation. Responding to these challenges, distributed evolutionary computation has received considerable attention over the past decade. This article provides a comprehensive survey of the state-of-the-art distributed evolutionary algorithms and models, which have been classified into two groups according to their task division mechanism. Population-distributed models are presented with master-slave, island, cellular, hierarchical, and pool architectures, which parallelize an evolution task at population, individual, or operation levels. Dimension-distributed models include coevolution and multi-agent models, which focus on dimension reduction. Insights into the models, such as synchronization, homogeneity, communication, topology, speedup, advantages and disadvantages are also presented and discussed. The study of these models helps guide future development of different and/or improved algorithms. Also highlighted are recent hotspots in this area, including the cloud and MapReduce-based implementations, GPU and CUDA-based implementations, distributed evolutionary multiobjective optimization, and real-world applications. Further, a number of future research directions have been discussed, with a conclusion that the development of distributed evolutionary computation will continue to flourish

Interaction Topologies and Information Flow

Networks are ubiquitous, underlying systems as diverse as the Internet, food webs, societal interactions, the cell, and the brain. Of crucial importance is the coupling of network structure with system dynamics, and much recent attention has focused on how information, such as pathogens, mutations, or ideas, ow through networks. In this dissertation, we advance the understanding of how network structure a ects information ow in two important classes of models. The rst is an independent interaction model, which is used to investigate the propagation of advantageous alleles in evolutionary algorithms. The second is a threshold model, which is used to study the dissemination of ideas, fads, and innovations throughout populations. This journal-format dissertation comprises three interrelated studies, in which we investigate the in uence of network structure on the dynamical properties of information ow. In the rst study, we develop an analytical technique to approximate system dynamics in arbitrarily structured regular interaction topologies. In the second study, we investigate the ow of advantageous alleles in degree-correlated scale-free population structures, and provide a simple topological metric for assessing the selective pressures induced by these networks. In the third study, we characterize the conditions in which global information cascades occur in threshold models of binary decisions with externalities, structured on degree-correlated Poisson-distributed random networks

Intelligent approaches to VLSI routing

Very Large Scale Integrated-circuit (VLSI) routing involves many large-size and complex problems and most of them have been shown to be NP-hard or NP-complete. As a result, conventional approaches, which have been successfully used to handle relatively small-size routing problems, are not suitable to be used in tackling large-size routing problems because they lead to \u27combinatorial explosion\u27 in search space. Hence, there is a need for exploring more efficient routing approaches to be incorporated into today\u27s VLSI routing system. This thesis strives to use intelligent approaches, including symbolic intelligence and computational intelligence, to solve three VLSI routing problems: Three-Dimensional (3-D) Shortest Path Connection, Switchbox Routing and Constrained Via Minimization. The 3-D shortest path connection is a fundamental problem in VLSI routing. It aims to connect two terminals of a net that are distributed in a 3-D routing space subject to technological constraints and performance requirements. Aiming at increasing computation speed and decreasing storage space requirements, we present a new A* algorithm for the 3-D shortest path connection problem in this thesis. This new A*algorithm uses an economical representation and adopts a novel back- trace technique. It is shown that this algorithm can guarantee to find a path if one exists and the path found is the shortest one. In addition, its computation speed is fast, especially when routed nets are spare. The computational complexities of this A* algorithm at the best case and the worst case are O(Ɩ) and 0(Ɩ3), respectively, where Ɩ is the shortest path length between the two terminals. Most importantly, this A\u27 algorithm is superior to other shortest path connection algorithms as it is economical in terms of storage space requirement, i.e., 1 bit/grid. The switchbox routing problem aims to connect terminals at regular intervals on the four sides of a rectangle routing region. From a computational point of view, the problem is NP-hard. Furthermore, it is extremely complicated and as the consequence no existing algorithm can guarantee to find a solution even if one exists no matter how high the complexity of the algorithm is. Previous approaches to the switch box routing problem can be divided into algorithmic approaches and knowledge-based approaches. The algorithmic approaches are efficient in computational time, but they are unsucessful at achieving high routing completion rate, especially for some dense and complicated switchbox routing problems. On the other hand, the knowledge-based approaches can achieve high routing completion rate, but they are not efficient in computation speed. In this thesis we present a hybrid approach to the switchbox routing problem. This hybrid approach is based on a new knowledge-based routing technique, namely synchronized routing, and combines some efficient algorithmic routing techniques. Experimental results show it can achieve the high routing completion rate of the knowledge-based approaches and the high efficiency of the algorithmic approaches. The constrained via minimization is an important optimization problem in VLSI routing. Its objective is to minimize the number of vias introduced in VLSI routing. From computational perspective, the constrained via minimization is NP-complete. Although for a special case where the number of wire segments splits at a via candidate is not more than three, elegant theoretical results have been obtained. For a general case in which there exist more than three wire segment splits at a via candidate few approaches have been proposed, and those approaches are only suitable for tackling some particular routing styles and are difficult or impossible to adjust to meet practical requirements. In this thesis we propose a new graph-theoretic model, namely switching graph model, for the constrained via minimization problem. The switching graph model can represent both grid-based and grid less routing problems, and allows arbitrary wire segments split at a via candidate. Then on the basis of the model, we present the first genetic algorithm for the constrained via minimization problem. This genetic algorithm can tackle various kinds of routing styles and be configured to meet practical constraints. Experimental results show that the genetic algorithm can find the optimal solutions for most cases in reasonable time

Algorithme génétique optimisant la propulsion de satellites pour le survol de sites terrestres

Cette recherche aborde le problème d'optimisation de la trajectoire d'un satellite de télédétection pour l'observation d'un ensemble de sites terrestres au cours d'une période donnée. Pour ce faire, le satellite tire avantage du contrôle de la période orbitale que lui procurent les propulseurs électriques à faible poussée. La planification de la trajectoire optimale de survol passe par la résolution de deux problèmes majeurs: en premier lieu la sélection adéquate d'un ensemble de points de survol et en second lieu l'interpolation optimale de la course orbitale du satellite liant les différents points de survol. Pour la sélection adéquate des points de survol, le projet met à contribution les techniques de l'intelligence artificielle et plus particulièrement les algorithmes génétiques. Le second problème est abordé de façon analytique. L'objectif est de développer une méthode (lui se combine facilement à l'algorithme génétique pour lui permettre de traiter le problème d'optimisation de trajectoire. Pour obtenir de bons résultats, la solution préconisée dans ce travail met en oeuvre un algorithme génétique hybride se combinant à la méthode du recuit simulé. La solution développée montre de bonnes capacités à répondre au problème d'optimisation de trajectoires de satellites pour le survol de sites terrestres

An adaptive parallel genetic algorithm.

Chi Wai Ho, Raymond.Thesis submitted in: December 1999.Thesis (M.Phil.)--Chinese University of Hong Kong, 2000.Includes bibliographical references (leaves 93-97).Abstracts in English and Chinese.Chapter Chapter 1 --- Introduction --- p.7Chapter 1.1 --- Thesis Outline --- p.10Chapter 1.2 --- Contribution at a Glance --- p.11Chapter Chapter 2 --- Background Concept and Related Work --- p.14Chapter 2.1 --- Genetic Algorithms (GAs) --- p.14Chapter 2.2 --- The Nature of GAs --- p.16Chapter 2.3 --- The Role of Mutation --- p.17Chapter 2.4 --- The Role of Crossover --- p.18Chapter 2.5 --- The Roles of the Mutation and Crossover Rates --- p.19Chapter 2.6 --- Adaptation of the Mutation and Crossover Rates --- p.19Chapter 2.7 --- Diversity Control --- p.21Chapter 2.8 --- Coarse-grain Parallel Genetic Algorithms --- p.25Chapter 2.9 --- Adaptation of Migration Period --- p.26Chapter 2.10 --- Serial and Parallel GAs --- p.27Chapter 2.11 --- Distributed Java Machine (DJM) --- p.28Chapter 2.12 --- Clustering --- p.30Chapter Chapter 3 --- Adaptation of the Mutation and Crossover Rates --- p.35Chapter 3.1 --- The Probabilistic Rule-based Adaptive Model (PRAM) --- p.35Chapter 3.2 --- Time Complexity --- p.37Chapter 3.3 --- Storage Complexity --- p.38Chapter Chapter 4 --- Diversity Control --- p.39Chapter 4.1 --- Repelling --- p.39Chapter 4.2 --- Implementation --- p.42Chapter 4.3 --- Lazy Repelling --- p.43Chapter 4.4 --- Repelling and Lazy Repelling with Deterministic Crowding --- p.43Chapter 4.5 --- Comparison of Repelling and Lazy Repelling with Recent Diversity Maintenance Models in Time Complexity --- p.44Chapter Chapter 5 --- An Adaptive Parallel Genetic Algorithm --- p.46Chapter 5.1 --- A Steady-State Genetic Algorithm --- p.46Chapter 5.2 --- An Adaptive Parallel Genetic Algorithm (aPGA) --- p.47Chapter 5.3 --- An Adaptive Parallel Genetic Algorithm for Clustering --- p.48Chapter 5.4 --- Implementation --- p.48Chapter 5.5 --- Time Complexity --- p.51Chapter Chapter 6 --- Performance Evaluation of PRAM --- p.52Chapter 6.1 --- Solution Quality --- p.58Chapter 6.2 --- Efficiency --- p.60Chapter 6.3 --- Discussion --- p.62Chapter Chapter 7 --- Performance Evaluation of Repelling --- p.66Chapter 7.1 --- Performance Comparison of Repelling and Lazy Repelling with Deterministic Crowding --- p.70Chapter 7.2 --- Performance Comparison with Recent Diversity Maintenance Models --- p.73Chapter 7.3 --- Performance Comparison with Serial and Parallel Gas --- p.75Chapter Chapter 8 --- Performance Evaluation of aPGA --- p.78Chapter 8.1 --- Scalability of Different Dimensionalities --- p.78Chapter 8.2 --- Speedup of Schwefel's function --- p.83Chapter 8.3 --- Solution Quality of Clustering Problems --- p.87Chapter 8.4 --- Speedup of The Clustering Problem --- p.89Chapter Chapter 9 --- Conclusion --- p.9

Implementación de un algoritmo genético paralelo sobre HW gráfico de última generación

Los algoritmos genéticos (AGs) son procedimientos de búsqueda y optimización inspirados por la simplicidad y efectividad del proceso de la evolución natural de las especies. Al igual que ocurre en la naturaleza, basan su éxito en la supervivencia de los individuos más aptos de una población. En este caso, un individuo es una solución potencial del problema, y se implementa como una estructura de datos. Los AGs trabajan sobre poblaciones de soluciones que evolucionan mediante la aplicación de operadores genéticos (selección, cruce y mutación) adecuados al problema específico que intentan resolver. Uno de los rasgos esenciales de los AGs es su paralelismo implícito puesto que, al igual que la evolución natural, trabajan con poblaciones enteras, no con sus individuos integrantes en particular. Los sistemas actuales cuentan con potentes tarjetas gráficas, frecuentemente programables, que permanecen inactivas durante la ejecución de aplicaciones no gráficas. Dichas tarjetas cuentan con un procesador de naturaleza paralela, que las hace especialmente indicadas para la ejecución de AGs. Este trabajo es una propuesta para aprovechar un recurso hardware habitualmente inactivo para implementar, en un sistema monoprocesador, algún tipo de topología de AGs paralelos. Obtenemos así mejoras -tanto en la calidad de las soluciones como en el tiempo de ejecución- con respecto a la ejecución secuencial del AG sobre la CPU. [ABSTRACT] Genetic algorithms (GAs) are optimization techniques which imitate the way that nature selects the best individuals (the best adaptation to the environment) to create descendants which are more highly adapted. The first step is to generate a random initial population, where each individual is represented by a character chain like a chromosome and with the greatest diversity, so that this population has the widest range of characteristics. Each individual represents a solution for the targeted problem. Then, each individual is evaluated using a fitness function, which indicates the quality of each individual. Finally, the best-adapted individuals are selected to generate a new population, whose average will be nearer to the desired solution. This new population is created making use of three operators: selection, crossover and mutation.One of the major aspects of GA is their ability to be parallelised. Indeed, because natural evolution deals with an entire population and not only with particular individuals, it is a remarkably highly parallel process. Nowadays computer systems incorporate powerful graphic cards that are commonly idle during a normal execution process of most of the optimization algorithms. Modern graphic cards use a pipelined streaming architecture to perform a significant part of the rendering process. Two stages in the pipelined process are programmable in current graphics hardware. The vertex engine is used to perform transformations on the vertex attributes (normal, position, color, texture, ...). On the other hand, the fragment engine is used to transform the fragments that form the different polygons. Both engines are extremely parallel, processing several elements in parallel and making extensive use of SIMD units. In this work we have presented a parallel implementation of a GA using a GPU. We have implemented not only three well know benchmarks problems with excellent Speed-up results, but also a novel implementation of an algorithm for solving defectives problems proposed in the literature

Multi-objective Digital VLSI Design Optimisation

Modern VLSI design's complexity and density has been exponentially increasing over the past 50 years and recently reached a stage within its development, allowing heterogeneous, many-core systems and numerous functions to be integrated into a tiny silicon die. These advancements have revealed intrinsic physical limits of process technologies in advanced silicon technology nodes. Designers and EDA vendors have to handle these challenges which may otherwise result in inferior design quality, even failures, and lower design yields under time-to-market pressure. Multiple or many design objectives and constraints are emerging during the design process and often need to be dealt with simultaneously. Multi-objective evolutionary algorithms show flexible capabilities in maintaining multiple variable components and factors in uncertain environments. The VLSI design process involves a large number of available parameters both from designs and EDA tools. This provides many potential optimisation avenues where evolutionary algorithms can excel. This PhD work investigates the application of evolutionary techniques for digital VLSI design optimisation. Automated multi-objective optimisation frameworks, compatible with industrial design flows and foundry technologies, are proposed to improve solution performance, expand feasible design space, and handle complex physical floorplan constraints through tuning designs at gate-level. Methodologies for enriching standard cell libraries regarding drive strength are also introduced to cooperate with multi-objective optimisation frameworks, e.g., subsequent hill-climbing, providing a richer pool of solutions optimised for different trade-offs. The experiments of this thesis demonstrate that multi-objective evolutionary algorithms, derived from biological inspirations, can assist the digital VLSI design process, in an industrial design context, to more efficiently search for well-balanced trade-off solutions as well as optimised design space coverage. The expanded drive granularity of standard cells can push the performance of silicon technologies with offering improved solutions regarding critical objectives. The achieved optimisation results can better deliver trade-off solutions regarding power, performance and area metrics than using standard EDA tools alone. This has been not only shown for a single circuit solution but also covered the entire standard-tool-produced design space

Algorithms in computer-aided design of VLSI circuits.

With the increased complexity of Very Large Scale Integrated (VLSI) circuits,Computer Aided Design (CAD) plays an even more important role. Top-downdesign methodology and layout of VLSI are reviewed. Moreover, previouslypublished algorithms in CAD of VLSI design are outlined.In certain applications, Reed-Muller (RM) forms when implemented withAND/XOR or OR/XNOR logic have shown some attractive advantages overthe standard Boolean logic based on AND/OR logic. The RM forms implementedwith OR/XNOR logic, known as Dual Forms of Reed-Muller (DFRM),is the Dual form of traditional RM implemented with AND /XOR.Map folding and transformation techniques are presented for the conversionbetween standard Boolean and DFRM expansions of any polarity. Bidirectionalmulti-segment computer based conversion algorithms are also proposedfor large functions based on the concept of Boolean polarity for canonicalproduct-of-sums Boolean functions. Furthermore, another two tabular basedconversion algorithms, serial and parallel tabular techniques, are presented forthe conversion of large functions between standard Boolean and DFRM expansionsof any polarity. The algorithms were tested for examples of up to 25variables using the MCNC and IWLS'93 benchmarks.Any n-variable Boolean function can be expressed by a Fixed PolarityReed-Muller (FPRM) form. In order to have a compact Multi-level MPRM(MMPRM) expansion, a method called on-set table method is developed.The method derives MMPRM expansions directly from FPRM expansions.If searching all polarities of FPRM expansions, the MMPRM expansions withthe least number of literals can be obtained. As a result, it is possible to findthe best polarity expansion among 2n FPRM expansions instead of searching2n2n-1 MPRM expansions within reasonable time for large functions. Furthermore,it uses on-set coefficients only and hence reduces the usage of memorydramatically.Currently, XOR and XNOR gates can be implemented into Look-Up Tables(LUT) of Field Programmable Gate Arrays (FPGAs). However, FPGAplacement is categorised to be NP-complete. Efficient placement algorithmsare very important to CAD design tools. Two algorithms based on GeneticAlgorithm (GA) and GA with Simulated Annealing (SA) are presented for theplacement of symmetrical FPGA. Both of algorithms could achieve comparableresults to those obtained by Versatile Placement and Routing (VPR) toolsin terms of the number of routing channel tracks